View ADT7475ARQZ-REEL_5126686.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

dbcool remote thermal monitor and fan controller adt7475 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005C2007 analog devices, inc. all rights reserved. features controls and monitors up to 4 fans high and low frequency fan drive signal 1 on-chip and 2 remote temperature sensors extended temperature measurement range, up to 191c automatic fan speed control mode controls system cooling based on measured temperature enhanced acoustic mode dramatically reduces user perception of changing fan speeds thermal protection feature via therm output monitors performance impact of intel pentium 4 processor thermal control circuit via therm input 3-wire and 4-wire fan speed measurement limit comparison of all monitored values meets smbus 2.0 electrical specifications (fully smbus 1.1 compliant) fully rohs compliant general description the adt7475 db cool? controller is a thermal monitor and multiple pwm fan controller for noise-sensitive or power- sensitive applications requiring active system cooling. the adt7475 can drive a fan using either a low or high frequency drive signal, monitor the temperature of up to two remote sensor diodes plus its own internal temperature, and measure and control the speed of up to four fans so that they operate at the lowest possible speed for minimum acoustic noise. the automatic fan speed control loop optimizes fan speed for a given temperature. the effectiveness of the systems thermal solution can be monitored using the therm input. the adt7475 also provides critical thermal protection to the system using the bidirectional therm pin as an output to prevent system or component overheating. functional block diagram 05381-001 band gap reference 10-bit adc value and limit registers limit comparators interrupt status registers gnd pwm1 pwm2 pwm3 pwm registers and controllers (hf and lf) acoustic enhancement control automatic fan speed control tach1 tach2 tach3 tach4 fan speed counter thermal protection performance monitoring therm input signal conditioning and analog multiplexer v cc to adt7475 v cc d1+ d1? d2+ d2? v ccp band gap temperature sensor interrupt masking pwm configuration registers address pointer register serial bus interface s c l sd a smbalert adt7475 figure 1.
adt7475 rev. b | page 2 of 68 table of contents features .............................................................................................. 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing diagram ........................................................................... 4 absolute maximum ratings............................................................ 5 thermal resistance ...................................................................... 5 esd caution.................................................................................. 5 pin configuration and function descriptions............................. 6 typical performance characteristics ............................................. 7 product description......................................................................... 9 quick comparison between adt7473 and adt7475 .......... 9 recommended implementation................................................. 9 serial bus interface......................................................................... 10 write operations ........................................................................ 11 read operations ......................................................................... 12 smbus timeout .......................................................................... 12 virus protection.......................................................................... 12 voltage measurement input...................................................... 12 analog-to-digital converter .................................................... 12 input circuitry............................................................................ 13 voltage measurement registers................................................ 13 v ccp limit registers ................................................................... 13 extended resolution registers ................................................. 13 additional adc functions for voltage measurements ........ 13 temperature measurement method ........................................ 15 factors affecting diode accuracy........................................... 17 additional adc functions for temperature measurement 18 limits, status registers, and interrupts....................................... 20 limit values ................................................................................ 20 interrupt status registers .......................................................... 21 therm timer ........................................................................... 23 fan drive using pwm control ............................................... 26 operating from 3.3 v standby ................................................. 31 standby mode ............................................................................. 31 xnor tree test mode .............................................................. 31 power-on default ...................................................................... 32 programming the automatic fan speed control loop ............ 33 automatic fan control overview............................................ 33 step 1: hardware configuration .............................................. 34 step 2: configuring the mux .................................................... 37 step 3: t min settings for thermal calibration channels ...... 39 step 4: pwm min for each pwm (fan) output ...................... 40 step 5: pwm max for pwm (fan) outputs.............................. 40 step 6: t range for temperature channels................................ 41 step 7: t therm for temperature channels ............................... 44 step 8: t hyst for temperature channels.................................. 45 register tables ................................................................................ 48 outline dimensions ....................................................................... 65 ordering guide .......................................................................... 65 revision history 11/07rev. a to rev. b changes to table 12........................................................................ 22 2/06rev. 0 to rev. a changes to table 1............................................................................ 3 changes to quick comparison between adt7473 and adt7475 section ............................................................................. 9 changes to analog-to-digital converter section...................... 13 changes to tach inputs section ................................................ 27 changes to fan speed measurement section ............................. 28 inserted figure 42........................................................................... 32 changes to power-on default section........................................ 32 changes to step 5: pmw max for pwm (fan) outputs section .............................................................................. 40 changes to table 14 ....................................................................... 48 changes to table 23 ....................................................................... 53 changes to table 43 ....................................................................... 60 7/05revision 0: initial version
adt7475 rev. b | page 3 of 68 specifications t a = t min to t max , v cc = v min to v max , unless otherwise noted. 1 table 1. parameter min typ max unit test conditions/comments power supply supply voltage 3.0 3.3 3.6 v supply current, i cc 1.5 3 ma interface inactive, adc active temperature-to-digital converter local sensor accuracy 0.5 1.5 c 0c t a 85c 2.5 c ?40c t a +125c resolution 0.25 c remote diode sensor accuracy 0.5 1.5 c 0c t a 85c 2.5 c ?40c t a +125c resolution 0.25 c remote sensor source current 180 a high level 11 ? low level analog-to-digital converter (including mux and attenuators) total unadjusted error (tue) 1.5 % differential nonlinearity (dnl) 1 lsb 8 bits power supply sensitivity 0.1 %/v conversion time (voltage input) 11 ms averaging enabled conversion time (local temperature) 12 ms averaging enabled conversion time (remote temperature) 38 ms averaging enabled total monitoring cycle time 145 ms averaging enabled 19 ms averaging disabled input resistance 70 120 k for v ccp channel fan rpm-to-digital converter accuracy 6 % 0c t a 70c 10 % ?40c t a +120c full-scale count 65,535 nominal input rpm 109 rpm fan count = 0xbfff 329 rpm fan count = 0x3fff 5000 rpm fan count = 0x0438 10,000 rpm fan count = 0x021c open-drain digital outputs (pwm1 to pwm3, xto) current sink, i ol 8.0 ma output low voltage, v ol 0.4 v i out = ?8.0 ma high level output current, i oh 0.1 20 a v out = v cc open-drain serial data bus output (sda) output low voltage, v ol 0.4 v i out = ?4.0 ma high level output current, i oh 0.1 1.0 a v out = v cc smbus digital inputs (scl, sda) input high voltage, v ih 2.0 v input low voltage, v il 0.4 v hysteresis 500 mv
adt7475 rev. b | page 4 of 68 parameter min typ max unit test conditions/comments digital input logic levels (tach inputs) input high voltage, v ih 2.0 v 3.6 v maximum input voltage input low voltage, v il 0.8 v ?0.3 v minimum input voltage hysteresis 0.5 v p-p digital input logic levels ( therm ) adtl+ input high voltage, v ih 0.75 v cc v input low voltage, v il 0.4 v digital input current input high current, i ih 1 a v in = v cc input low current, i il 1 a v in = 0 v input capacitance, c in 5 pf serial bus timing 2 see figure 2 clock frequency, f sclk 10 400 khz glitch immunity, t sw 50 ns bus free time, t buf 4.7 s scl low time, t low 4.7 s scl high time, t high 4.0 50 s scl, sda rise time, t r 1000 ns scl, sda fall time, t f 300 s data setup time, t su: dat 250 ns detect clock low timeout, t timeout 15 35 ms can be optionally disabled 1 all voltages are measured with respect to gnd, unless otherwise specified. typicals are at t a = 25c and represent the most likely parametric norm. logic inputs accept input high voltages of up to v max , even when the device is operating down to v min . timing specifications are tested at logic levels of v il = 0.8 v for a falling edge and v ih = 2.0 v for a rising edge. 2 smbus timing specifications are guaranteed by design and are not production tested. timing diagram scl sd a ps sp t buf t hd: sta t hd: dat t su: dat t f t r t low t su: sta t high t hd: sta t su: sto 05381-002 figure 2. serial bus timing diagram
adt7475 rev. b | page 5 of 68 absolute maximum ratings table 2. parameter rating positive supply voltage (v cc ) 3.6 v voltage on any input or output pin ?0.3 v to +3.6 v input current at any pin 5 ma package input current 20 ma maximum junction temperature (t jmax ) 150c storage temperature range ?65c to +150c lead temperature, soldering ir reflow peak temperature 260c lead temperature (soldering 10 sec) 300c esd rating 1500 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja jc unit 16-lead qsop package 150 39 c/w esd caution
adt7475 rev. b | page 6 of 68 pin configuration and fu nction descriptions 05381-003 pwm2/smbalert tach4/therm/gpio/smbalert 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 gnd v cc tach3 tach2 tach1 scl pwm1/xto v ccp d1+ d2? pwm3 d2+ d1? sda top view (not to scale) adt7475 figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 scl digital input (open drain). smbus serial clock input. requires smbus pull-up. 2 gnd ground pin. 3 v cc power supply. v cc is also monitored through this pin. 4 tach3 digital input (open drain). fan tachometer input to measure speed of fan 3. 5 pwm2 pwm2: digital output (open drain). requires 10 k typical pull-up. pulse-width modulated output to control fan 2 speed. can be configured as a high or low frequency drive. smbalert smbalert : digital output (open drain). this pin can be reconfigured as an smbalert interrupt output to signal out-of-limit conditions. 6 tach1 digital input (open drain). fan tachometer input to measure the speed of fan 1. 7 tach2 digital input (open drain). fan tachometer input to measure the speed of fan 2. 8 pwm3 digital i/o (open drain). pulse-width modulated output to control the speed of fan 3 and fan 4. requires 10 k typical pull-up. can be configured as a high or low frequency drive. 9 tach4 tach4: digital input (open drain). fan ta chometer input to measure the speed of fan 4. therm therm : digital i/o (open drain). alternatively, this pin can be reconfigured as a bidirectional therm pin that can be used to time an d monitor assertions on the therm input. for example, the pin can be connected to the prochot output of an intel? pentium? 4 proces sor or to the output of a trip point temperature sensor. this pin can be used as an output to signal overtemperature conditions. gpio gpio: general-purpose open drain digital i/o. smbalert smbalert : digital output (open drain). this pin can be reconfigured as an smbalert interrupt output to signal out-of-limit conditions. 10 d2? cathode connection to second thermal diode. 11 d2+ anode connection to second thermal diode. 12 d1? cathode connection to first thermal diode. 13 d1+ anode connection to first thermal diode. 14 v ccp analog input. monito rs processor core voltage (0 v to 3 v). 15 pwm1 digital output (open drain). pulse-width modulated output to control fan 1 speed. requires 10 k typical pull-up. xto also functions as the output from the xnor tree in xnor test mode. 16 sda digital i/o (open drain). smbus bidirectional serial data. requires 10 k typical pull-up.
adt7475 rev. b | page 7 of 68 typical performance characteristics 0 ?10 ?20 ?30 ?40 ?50 ?60 024681012 capacitance (nf) tempe r a ture error (c) 14 16 18 20 22 05381-004 figure 4. temperature error vs. capacitance between d+ and d? 30 20 10 0 ?10 ?20 ?30 02 04 06 0 leakage resistance (m ? ) temper a ture error (c) 80 100 ?40 05381-005 d+ to v cc d+ to gnd figure 5. remote temperature error vs. pcb resistance 30 25 20 15 10 5 0 ?5 0 100m 200m 300m 400m 500m 600m noise frequency (hz) temper a ture error (c) 100mv 60mv 40mv 05381-006 figure 6. remote temperature error vs. common-mode noise frequency 70 60 50 40 30 20 0 10 0 100m 200m 300m 400m 500m 600m noise frequency (hz) temper a ture error (c) 40mv 05381-007 ?10 60mv 100mv figure 7. remote temperature error vs. differential mode noise frequency 1.20 1.18 1.16 1.14 1.12 1.10 1.08 1.06 3.0 3.1 3.2 3.3 3.4 v dd (v) i dd (ma) 1.04 1.02 3.5 3.6 1.00 0.98 05381-008 figure 8. normal i dd vs. power supply 100mv 250mv 15 10 5 0 ?5 ?10 ?15 0 100m 200m 300m 400m 500m 600m frequency (hz) temper a ture error (c) 05381-009 figure 9. internal temperature error vs. power supply noise
adt7475 rev. b | page 8 of 68 05381-010 6 4 2 0 ?2 ?4 ?6 0 100m 200m 300m frequency (hz) temper a ture error (c) 400m 500m 600m ?8 ?10 ?12 100mv 250mv figure 10. remote temperature error vs. power supply noise frequency 3.0 2.5 2.0 1.5 1.0 0.5 0 ?0.5 ?40 ?20 0 20 40 60 85 oil bath temperature (c) temper a ture error (c) ?1.0 ?1.5 105 125 05381-011 figure 11. internal temperature error vs. adt7475 temperature 3.0 2.5 2.0 1.5 1.0 0.5 0 ?0.5 ?40 ?20 0 20 40 60 85 oil bath temperature (c) temper a ture error (c) ?1.0 ?1.5 105 125 05381-012 ?2.0 figure 12. remote temperature error vs. adt7475 temperature
adt7475 rev. b | page 9 of 68 product description the adt7475 is a complete thermal monitor and multiple fan controller for any system requiring thermal monitoring and cooling. the device communicates with the system via a serial system management bus. the serial bus controller has a serial data line for reading and writing addresses and data (pin 16), and an input line for the serial clock (pin 1). all control and programming functions for the adt7475 are performed over the serial bus. in addition, a pin can be reconfigured as an smbalert output to signal out-of-limit conditions. quick comparison between adt7473 and adt7475 ? the adt7473 supports advanced dynamic t min features while the adt7475 does not. ? acoustic smoothing is improved on the adt7475. ? therm can be selected as an output only on the adt7475. ? the adt7475 has two additional configuration registers. ? the adt7475 has other minor register changes. the adt7475 is similar to the adt7473 in that it is powered by a supply no greater than 3.6 v. exceeding this specification results in irreversible damage to the adt7475. signal pins (tach/pwm) should be pulled up or clamped to 3.6 v maximum. see the specifications section for more information. recommended implementation configuring the adt7475 as shown in figure 13 allows the system designer to use the following features: ? two pwm outputs for fan control of up to three fans (the front and rear chassis fans are connected in parallel). ? three tach fan speed measurement inputs. ? v cc measured internally through pin 3. ? cpu temperature measured using the remote 1 temperature channel. ? ambient temperature measured through the remote 2 temperature channel. ? bidirectional therm pin. this feature allows intel pentium 4 prochot monitoring and can function as an overtemperature therm output. the therm pin can alternatively be programmed as an smbalert system interrupt output. 05381-015 tach2 pwm3 tach3 d1+ d1? gnd adt7475 scl sda tach1 pwm1 cpu fan ambient temperature smbalert d2+ d2? therm prochot front chassis fan rear chassis fan cpu ich figure 13. adt7475 configuration
adt7475 rev. b | page 10 of 68 serial bus interface on pcs and servers, control of the adt7475 is carried out using the smbus. the adt7475 is connected to this bus as a slave device under the control of a master controller, which is usually (but not necessarily) the ich. the adt7475 has a fixed 7-bit serial bus address of 0101110 or 0x2e. the read/write bit must be added to get the 8-bit address (01011100 or 0x5c). data is sent over the serial bus in sequences of nine clock pulses, that is, eight bits of data followed by an acknowledge bit from the slave device. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period because a low-to-high transition when the clock is high may be interpreted as a stop signal. the number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. when all data bytes are read or written, stop conditions are established. in write mode, the master pulls the data line high during the tenth clock pulse to assert a stop condition. in read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse; this is known as no acknowledge. the master takes the data line low during the low period before the tenth clock pulse, and then high during the tenth clock pulse to assert a stop condition. any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. in the adt7475, write operations contain either one or two bytes, and read operations contain one byte. to write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed, and then data can be written to that register or read from it. the first byte of a write operation always contains an address that is stored in the address pointer register. if data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the address pointer register. this write operation is shown in figure 14 . the device address is sent over the bus, and then r/ w is set to 0. this is followed by two data bytes. the first data byte is the address of the internal data register to write to, which is stored in the address pointer register. the second data byte is the data to write to the internal data register. when reading data from a register, there are two possibilities: ? if the adt7475 address pointer register value is unknown or not the desired value, it must first be set to the correct value before data can be read from the desired data register. this is done by performing a write to the adt7475 as before, but only the data byte containing the register address is sent, because no data is written to the register (see figure 15 ). a read operation is then performed consisting of the serial bus address; the r/ w bit set to 1, followed by the data byte read from the data register (see figure 16 ). ? if the address pointer register is known to be already at the desired address, data can be read from the corresponding data register without first writing to the address pointer register (see figure 16 ). r/w 0 scl s da 10 1 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 ack. by adt7475 start by master 19 1 ack. by adt7475 9 d7 d6 d5 d4 d3 d2 d1 d0 ack. by adt7475 stop by master 1 9 scl (continued) sda (continued) frame 1 serial bus address byte frame 2 address pointer register byte frame 3 data byte 0 5381-016 figure 14. writing a register address to the address pointe r register, then writing data to the selected register
adt7475 rev. b | page 11 of 68 r/w 0 scl sda 10 1 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 ack. by adt7475 stop by master start by master frame 1 serial bus address byte frame 2 address pointer register byte 1 19 ack. by adt7475 9 05381-017 figure 15. writing to the address pointer register only r/w 0 scl sda 10 1 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 no ack. by master stop by master start by master frame 1 serial bus address byte frame 2 data byte from adt745 1 19 ack. by adt7475 9 05381-018 figure 16. reading data from a previously selected register it is possible to read a data byte from a data register without first writing to the address pointer register if the address pointer register is already at the correct value. however, it is not possible to write data to a register without writing to the address pointer register because the first data byte of a write is always written to the address pointer register. in addition to supporting the send byte and receive byte pro- tocols, the adt7475 also supports the read byte protocol (for more information, see system management bus specifications rev. 2.0 , available from intel). if several read or write operations must be performed in succession, the master can send a repeat start condition instead of a stop condition to begin a new operation. write operations the smbus specification defines several protocols for differ- ent types of read and write operations. the ones used in the adt7475 are discussed in this section. the following abbreviations are used in the diagrams: sstart pstop rread wwrite aacknowledge a no acknowledge the adt7475 uses the following smbus write protocols. send byte in this operation, the master device sends a single command byte to a slave device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code. 5. the slave asserts ack on sda. 6. the master asserts a stop condition on sda and the transaction ends. for the adt7475, the send byte protocol is used to write a register address to ram for a subsequent single-byte read from the same address. this operation is shown in figure 17 . 05381-019 slave address wa sa register address 23 15 4 p 6 figure 17. setting a register address for a subsequent read if the master is required to read data from the register immedi- ately after setting up the address, it can assert a repeat start condition immediately after the final ack and carry out a single-byte read without asserting an intermediate stop condition. write byte in this operation, the master device sends a command byte and one data byte to the slave device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts ack on sda. 4. the master sends a command code. 5. the slave asserts ack on sda. 6. the master sends a data byte. 7. the slave asserts ack on sda. 8. the master asserts a stop condition on sda and the transaction ends. the byte write operation is shown in figure 18 . 05381-020 slave address wa data sa register address 23 15 4 a p 6 7 8 figure 18. single-byte write to a register
adt7475 rev. b | page 12 of 68 read operations the adt7475 uses the following smbus read protocols. receive byte this operation is useful when repeatedly reading a single register. the register address must be set up previously. in this operation, the master device receives a single byte from a slave device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the read bit (high). 3. the addressed slave device asserts ack on sda. 4. the master receives a data byte. 5. the master asserts no ack on sda. 6. the master asserts a stop condition on sda, and the transaction ends. in the adt7475, the receive byte protocol is used to read a single byte of data from a register whose address has previously been set by a send byte or write byte operation. this operation is shown in figure 19 . 0 5381-021 slave address data ar sa 24 3 15 p 6 figure 19. single-byte read from a register alert response address alert response address (ara) is a feature of smbus devices that allows an interrupting device to identify itself to the host when multiple devices exist on the same bus. the smbalert output can be used as either an interrupt output or an smbalert . one or more outputs can be connected to a common smbalert line connected to the master. if a devices smbalert line goes low, the following events occur: 1. smbalert is pulled low. 2. the master initiates a read operation and sends the alert response address (ara = 0001 100). this general call address must not be used as a specific device address. 3. the device whose smbalert output is low responds to the alert response address, and the master reads its device address. the address of the device is now known and can be interrogated in the usual way. 4. if more than one devices smbalert output is low, the one with the lowest device address has priority in accor- dance with normal smbus arbitration. 5. once the adt7475 has responded to the alert response address, the master must read the status registers, and the smbalert is cleared only if the error condition has gone away. smbus timeout the adt7475 includes an smbus timeout feature. if there is no smbus activity for 35 ms, the adt7475 assumes that the bus is locked and releases the bus. this prevents the device from locking or holding the smbus expecting data. some smbus controllers cannot handle the smbus timeout feature, so it can be disabled. configuration register 1 (0x40) bit 6 todis = 0; smbus timeout enabled (default). bit 6 todis = 1; smbus timeout disabled. virus protection to prevent rogue programs or viruses from accessing critical adt7475 register settings, the lock bit can be set. setting bit 1 of configuration register 1 (0x40) sets the lock bit and locks critical registers. in this mode, certain registers can no longer be written to until the adt7475 is powered down and powered up again. for more information on which registers are locked, see the register tables section. voltage measurement input the adt7475 has one external voltage measurement channel. it can also measure its own supply voltage, v cc . pin 14 can measure v ccp . the v cc supply voltage measurement is carried out through the v cc pin (pin 3). the v ccp input can be used to monitor a chipset supply voltage in computer systems. analog-to-digital converter all analog inputs are multiplexed into the on-chip, successive approximation, analog-to-digital converter. this has a resolu- tion of 10 bits. the basic input range is 0 v to 2.25 v, but the input has built-in attenuators to allow measurement of v ccp without any external components. to allow for the tolerance of the supply voltage, the adc produces an output of 3/4 full scale (decimal 768 or 300 hex) for the nominal input voltage and so has adequate headroom to deal with overvoltages.
adt7475 rev. b | page 13 of 68 input circuitry the internal structure for the v ccp analog input is shown in figure 20 . the input circuit consists of an input protection diode, an attenuator, and a capacitor to form a first-order, low- pass filter that gives the input immunity to high frequency noise. 05381-022 v ccp 17.5k ? 52.5k ? 35pf figure 20. structure of analog inputs voltage measurement registers register 0x21, v ccp reading = 0x00 default register 0x22, v cc reading = 0x00 default v ccp limit registers associated with the v ccp measurement channel is a high and low limit register. exceeding the programmed high or low limit causes the appropriate status bit to be set. exceeding either limit can also generate smbalert interrupts. register 0x46, v ccp low limit = 0x00 default register 0x47, v ccp high limit = 0xff default table 6 shows the input ranges of the analog inputs and output codes of the 10-bit adc. when the adc is running, it samples and converts a voltage input in 711 s and averages 16 conversions to reduce noise; a measurement takes nominally 11.38 ms. extended resolution registers voltage measurements can be made with higher accuracy using the extended resolution registers (0x76 and 0x77). whenever the extended resolution registers are read, the corresponding data in the voltage measurement registers is locked until their data is read. that is, if extended resolution is required, then the extended resolution register must be read first, immediately followed by the appropriate voltage measurement register. additional adc functions for voltage measurements a number of other functions are available on the adt7475 to offer the system designer increased flexibility. turn-off averaging for each voltage measurement read from a value register, 16 readings have been made internally, and the results averaged, before being placed into the value register. for instances where faster conversions are needed, setting bit 4 of configuration register 2 (0x73) turns averaging off. this effectively gives a reading 16 times faster (711 s), but the reading may be noisier. bypass voltage input attenuator setting bit 5 of configuration register 2 (0x73) removes the attenuation circuitry from the v ccp input. this allows the user to directly connect external sensors or to rescale the analog voltage measurement inputs for other applications. the input range of the adc without the attenuators is 0 v to 2.25 v. single-channel adc conversion setting bit 6 of configuration register 2 (0x73) places the adt7475 into single-channel adc conversion mode. in this mode, the adt7475 can be made to read a single voltage chan- nel only. if the internal adt7475 clock is used, the selected input is read every 711 s. the appropriate adc channel is selected by writing to bits [7:5] of the tach1 minimum high byte register (0x55). table 5. single-channel adc conversion register 0x55, bits [7:5] channel selected 001 v ccp 010 v cc 101 remote 1 temperature 110 local temperature 111 remote 2 temperature configuration register 2 (0x73) bit 4 = 1; averaging off. bit 5 = 1; bypass input attenuators. bit 6 = 1; single-channel convert mode. tach1 minimum high byte (0x55) bits [7:5] select the adc channel for single-channel convert mode.
adt7475 rev. b | page 14 of 68 table 6. 10-bit adc output code vs. v in input voltage adc output v cc (3.3 v in ) 1 v ccp decimal binary (10 bits) <0.0042 <0.00293 0 00000000 00 0.0042 to 0.0085 0.0293 to 0.0058 1 00000000 01 0.0085 to 0.0128 0.0058 to 0.0087 2 00000000 10 0.0128 to 0.0171 0.0087 to 0.0117 3 00000000 11 0.0171 to 0.0214 0.0117 to 0.0146 4 00000001 00 0.0214 to 0.0257 0.0146 to 0.0175 5 00000001 01 0.0257 to 0.0300 0.0175 to 0.0205 6 00000001 10 0.0300 to 0.0343 0.0205 to 0.0234 7 00000001 11 0.0343 to 0.0386 0.0234 to 0.0263 8 00000010 00 ? ? ? 1.100 to 1.1042 0.7500 to 0.7529 256 (1/4-scale) 01000000 00 ? ? ? 2.200 to 2.2042 1.5000 to 1.5029 512 (1/2-scale) 10000000 00 ? ? ? 3.300 to 3.3042 2.2500 to 2.2529 768 (3/4 scale) 11000000 00 ? ? ? 4.3527 to 4.3570 2.9677 to 2.9707 1013 11111101 01 4.3570 to 4.3613 2.9707 to 2.9736 1014 11111101 10 4.3613 to 4.3656 2.9736 to 2.9765 1015 11111101 11 4.3656 to 4.3699 2.9765 to 2.9794 1016 11111110 00 4.3699 to 4.3742 2.9794 to 2.9824 1017 11111110 01 4.3742 to 4.3785 2.9824 to 2.9853 1018 11111110 10 4.3785 to 4.3828 2.9853 to 2.9882 1019 11111110 11 4.3828 to 4.3871 2.9882 to 2.9912 1020 11111111 00 4.3871 to 4.3914 2.9912 to 2.9941 1021 11111111 01 4.3914 to 4.3957 2.9941 to 2.9970 1022 11111111 10 >4.3957 >2.9970 1023 11111111 11 1 the v cc output codes listed assume that v cc is 3.3 v and that v cc should never exceed 3.6 v.
adt7475 rev. b | page 15 of 68 temperature measurement method local temperature measurement the adt7475 contains an on-chip band gap temperature sensor whose output is digitized by the on-chip, 10-bit adc. the 8-bit msb temperature data is stored in the temperature registers (0x25, 0x26, and 0x27). because both positive and negative temperatures can be measured, the temperature data is stored in offset 64 format or twos complement format, as shown in table 7 and table 8 . theoretically, the temperature sensor and adc can measure temperatures from ?128c to +127c (or ?64c to +191c in the extended temperature range) with a resolution of 0.25c. however, this exceeds the operating temperature range of the device, so local temperature measurements outside the adt7475 operating temperature range are not possible. remote temperature measurement the adt7475 can measure the temperature of two remote diode sensors or diode-connected tran sistors connected to pin 10 and pin 11 or to pin 12 and pin 13. the forward voltage of a diode or diode-connected transistor operated at a constant current exhibits a negative temperature coefficient of about C2 mv/c. because the absolute value of v be varies from device to device and individual calibration is required to null this out, the technique is unsuitable for mass production. 05381-023 d+ bias diode v dd to adc v out+ v out? remote sensing transistor d? thermda thermdc i n i i bias low-pass filter f c = 65khz cpu figure 21. signal conditioning for remote diode temperature sensors
adt7475 rev. b | page 16 of 68 the technique used in the adt7475 is to measure the change in v be when the device is operated at two different currents. this is given by v be = kt / q ln(n) where: k is boltzmanns constant. q is the charge on the carrier. t is the absolute temperature in kelvin. n is the ratio of the two currents. figure 21 shows the input signal conditioning used to measure the output of a remote temperature sensor. this figure shows the external sensor as a substrate transistor, provided for temperature monitoring on some microprocessors. it could also be a discrete transistor such as a 2n3904/2n3906. if a discrete transistor is used, the collector is not grounded and should be linked to the base. if a pnp transistor is used, the base is connected to the d? input and the emitter to the d+ input. if an npn transistor is used, the emitter is connected to the d? input and the base to the d+ input. figure 22 and figure 23 show how to connect the adt7475 to an npn or pnp transistor for temperature measurement. to prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground but is biased above ground by an internal diode at the d? input. to measure v be , the sensor is switched between operating currents of i and n i. the resulting waveform is passed through a 65 khz low-pass filter to remove noise and to a chopper-stabilized amplifier th at performs the functions of amplification and rectification of the waveform to produce a dc voltage proportional to v be . this voltage is measured by the adc to give a temperature output in 10-bit, twos complement format. to further reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles. a remote temperature measurement takes nominally 38 ms. the results of remote temperature meas urements are stored in 10-bit, twos complement format, as shown in table 7 . the extra resolu- tion for the temperature measurements is held in the extended resolution register 2 (0x77). this gives temperature readings with a resolution of 0.25c. noise filtering for temperature sensors operating in noisy environments, previous practice was to place a capacitor across the d+ pin and d? pin to help combat the effects of noise. however, large capaci- tances affect the accuracy of the temperature measurement, leading to a recommended maximum capacitor value of 1000 pf. this capacitor reduces the noise but does not eliminate it. sometimes, this sensor noise is a problem in a very noisy environment. in most cases, a capacitor is not required because differential inputs, by their very nature, have a high immunity to noise. 2 n3904 npn adt7475 d+ d? 05381-025 figure 22. measuring temperature using an npn transistor 2 n3906 pnp adt7475 d+ d? 05381-026 figure 23. measuring temperature using a pnp transistor
adt7475 rev. b | page 17 of 68 factors affecting diode accuracy remote sensing diode the adt7475 is designed to work with either substrate transistors built into processors or with discrete transistors. substrate transistors are generally pnp types with the collector connected to the substrate. discrete types can be either pnp or npn transistors connected as a diode (base-shorted to the collector). if an npn transistor is used, the collector and base are connected to d+ and the emitter to d?. if a pnp transistor is used, the collector and base are connected to d? and the emitter is connected to d+. to reduce the error due to variations in both substrate and discrete transistors, a number of factors should be taken into consideration: ? the ideality factor, n f , of the transistor is a measure of the deviation of the thermal diode from ideal behavior. the adt7475 is trimmed for an n f value of 1.008. use the following equation to calculate the error introduced at a temperature, t (c), when using a transistor whose n f does not equal 1.008. see the processor data sheet for the n f values. t = ( n f ? 1.008) (273.15 k + t ) to factor this in, the user can write the t value to the offset register. the adt7475 automatically adds it to or subtracts it from the temperature measurement. ? some cpu manufacturers specify the high and low current levels of the substrate transistors. the high current level of the adt7475, i high , is 180 a and the low level current, i low , is 11 a. if the adt7475 current levels do not match the current levels specified by the cpu manufacturer, it might be necessary to remove an offset. the cpus data sheet advises whether this offset needs to be removed and how to calculate it. this offset can be programmed to the offset register. if more than one offset must be considered, the algebraic sum of these offsets must be programmed to the offset register. if a discrete transistor is used with the adt7475, the best accuracy is obtained by choosing devices according to the following criteria: ? base-emitter voltage greater than 0.25 v at 11 a, at the highest operating temperature. ? base-emitter voltage less than 0.95 v at 180 a, at the lowest operating temperature. ? base resistance less than 100 . ? small variation in h fe (approximately 50 to 150) that indicates tight control of v be characteristics. transistors, such as 2n3904, 2n3906, or equivalents in sot-23 packages, are suitable devices to use. table 7. twos complement temperature data format temperature digital output (10-bit) 1 C128c 1000 0000 00 (diode fault) C50c 1100 1110 00 C25c 1110 0111 00 C10c 1111 0110 00 0c 0000 0000 00 10.25c 0000 1010 01 25.5c 0001 1001 10 50.75c 0011 0010 11 75c 0100 1011 00 100c 0110 0100 00 125c 0111 1101 00 127c 0111 1111 00 1 bold numbers denote 2 lsbs of measurement in extended resolution register 2 (0x77) with 0.25c resolution. table 8. extended range temperature data format temperature digital output (10-bit) 1 C64c 0000 0000 00 (diode fault) C1c 0011 1111 00 0c 0100 0000 00 1c 0100 0001 00 10c 0100 1010 00 25c 0101 1001 00 50c 0111 0010 00 75c 1000 1001 00 100c 1010 0100 00 125c 1011 1101 00 191c 1111 1111 00 1 bold numbers denote 2 lsbs of measurement in extended resolution register 2 (0x77) with 0.25c resolution. nulling out temperature errors as cpus run faster, it is more difficult to avoid high frequency clocks when routing the d+/dC traces around a system board. even when recommended layout guidelines are followed, some temperature errors can still be attributable to noise coupled onto the d+/dC lines. constant high frequency noise usually attenuates, or increases, temperature measurements by a linear, constant value. the adt7475 has two temperature offset registers, register 0x70 and register 0x72, for the remote 1 and remote 2 temperature channels. by doing a one-time calibration of the system, the user can determine the offset caused by system board noise and null it out using the offset registers. the offset registers automatically add a twos complement 8-bit reading to every temperature measurement.
adt7475 rev. b | page 18 of 68 changing bit 1 of configuration register 5 (0x7c) changes the resolution and therefore the range of the temperature offset as either having a range of C63c to +127c, with a resolution of 1c, or having a range of ?63c to +64c, with a resolution of 0.5c. this temperature offset can be used to compensate for linear temperature errors introduced by noise. temperature offset registers register 0x70, remote 1 temperature offset = 0x00 (0c default) register 0x71, local temperature offset = 0x00 (0c default) register 0x72, remote 2 temperature offset = 0x00 (0c default) adt7463/adt7475 backwards compatible mode by setting bit 0 of configuration register 5 (0x7c), all tempera- ture measurements are stored in the zone temperature value registers (0x25, 0x26, and 0x27) in twos complement in the range ?128c to +127c. the temperature limits must be reprogrammed in twos complement. if a twos complement temperature below ?128c is entered, the temperature is clamped to ?128c. in this mode, the diode fault condition remains ?128c = 1000 0000, while in the extended temperature range (?64c to +191c), the fault condition is represented by ?64c = 0000 0000. temperature measurement registers register 0x25, remote 1 temperature register 0x26, local temperature register 0x27, remote 2 temperature register 0x77, extended resolution 2 = 0x00 default bits [7:6] tdm2, remote 2 temperature lsbs. bits [5:4] ltmp, local temperature lsbs. bits [3:2] tdm1, remote 1 temperature lsbs. temperature measurement limit registers associated with each temperature measurement channel are high and low limit registers. exceeding the programmed high or low limit causes the appropriate status bit to be set. exceeding either limit can also generate smbalert interrupts (depending on the way the interrupt mask register is programmed and assuming that smbalert is set as an output on the appropriate pin). register 0x4e, remote 1 temperature low limit = 0x81 default register 0x4f, remote 1 temperature high limit = 0x7f default register 0x50, local temperature low limit = 0x81 default register 0x51, local temperature high limit = 0x7f default register 0x52, remote 2 temperature low limit = 0x81 default register 0x53, remote 2 temperature high limit = 0x7f default reading temperature from the adt7475 it is important to note that temperature can be read from the adt7475 as an 8-bit value (with 1c resolution) or as a 10-bit value (with 0.25c resolution). if only 1c resolution is required, the temperature readings can be read back at any time and in no particular order. if the 10-bit measurement is required, this involves a two- register read for each measurement. the extended resolution register 2 (0x77) should be read first. this causes all temperature reading registers to be frozen until all temperature reading registers have been read from. this prevents an msb reading from being updated while its two lsbs are being read and vice versa. additional adc functions for temperature measurement a number of other functions are available on the adt7475 to offer the system designer increased flexibility. turn-off averaging for each temperature measurement read from a value register, 16 readings have actually been made internally, and the results averaged, before being placed into the value register. sometimes it is necessary to take a very fast measurement. setting bit 4 of configuration register 2 (0x73) turns averaging off. the default round-robin cycle time takes 146.5 ms. table 9. conversion time with averaging disabled channel measurement time (ms) voltage channels 0.7 remote temperature 1 7 remote temperature 2 7 local temperature 1.3 when bit 7 of configuration register 6 (0x10) is set, the default round-robin cycle time increases to 240 ms. table 10. conversion time with averaging enabled channel measurement time (ms) voltage channels 11 remote temperature 1 39 remote temperature 2 39 local temperature 12
adt7475 rev. b | page 19 of 68 single-channel adc conversions setting bit 6 of configuration register 2 (0x73) places the adt7475 into single-channel adc conversion mode. in this mode, the adt7475 can be made to read a single temperature channel only. the appropriate adc channel is selected by writing to bits [7:5] of the tach1 minimum high byte register (0x55). table 11. programming single-channel adc mode for temperatures register 0x55, bits [7:5] channel selected 101 remote 1 temperature 110 local temperature 111 remote 2 temperature configuration register 2 (0x73) bit 4 = 1, averaging off. bit 6 = 1, single-channel convert mode. tach1 minimum high byte register ( 0x55) bits [7:5] select the adc channel for single-channel convert mode. overtemperature events overtemperature events on any of the temperature channels can be detected and dealt with automatically in automatic fan speed control mode. register 0x6a to register 0x6c are the therm temperature limit registers. when a temperature exceeds its therm temperature limit, all pwm outputs run at the maximum pwm duty cycle (register 0x38, register 0x39, and register 0x3a). this effectively runs the fans at the fastest allowed speed. the fans run at this speed until the temperature drops below therm minus hysteresis. this can be disabled by setting the boost bit in configuration register 3 (0x78), bit 2. the hysteresis value for the therm temperature limit is the value programmed into register 0x6d and register 0x6e (hysteresis registers). the default hysteresis value is 4c. fans temperature 100% hysteresis (c) therm limit 05381-027 figure 24. therm temperature limit operation therm can be disabled on specific temperature channels using bits [7:5] of configuration register 5 (0x7c). therm can also be disabled by ? in offset 64 mode, writing ?64c to the appropriate therm temperature limit. ? in twos complement mode , writing ?128c to the appropriate therm temperature limit.
adt7475 rev. b | page 20 of 68 limits, status registers, and interrupts limit values associated with each measurement channel on the adt7475 are high and low limits. these can form the basis of system status monitoring; a status bit can be set for any out-of-limit condition and detected by polling the device. alternatively, smbalert interrupts can be generated to flag out-of-limit conditions to a processor or microcontroller. 8-bit limits the following is a list of 8-bit limits on the adt7475. voltage l imit re gisters register 0x46, v ccp low limit = 0x00 default register 0x47, v ccp high limit = 0xff default register 0x48, v cc low limit = 0x00 default register 0x49, v cc high limit = 0xff default temperature limit registers register 0x4e, remote 1 temperature low limit = 0x81 default register 0x4f, remote 1 temperature high limit = 0x7f default register 0x6a, remote 1 therm temperature limit = 0x64 default register 0x50, local temperature low limit = 0x81 default register 0x51, local temperature high limit = 0x7f default register 0x6b, local therm temperature limit = 0x64 default register 0x52, remote 2 temperature low limit = 0x81 default register 0x53, remote 2 temperature high limit = 0x7f default register 0x6c, remote 2 therm temperature limit = 0x64 default therm limit register register 0x7a, therm timer limit = 0x00 default 16-bit limits the fan tach measurements are 16-bit results. the fan tach limits are also 16 bits, consisting of a high byte and low byte. because fans running under speed or stalled are normally the only conditions of interest, only high limits exist for fan tachs. because the fan tach period is actually being measured, exceeding the limit indicates a slow or stalled fan. fan limit registers register 0x54, tach1 minimum low byte = 0xff default register 0x55, tach1 minimum high byte = 0xff default register 0x56, tach2 minimum low byte = 0xff default register 0x57, tach2 minimum high byte = 0xff default register 0x58, tach3 minimum low byte = 0xff default register 0x59, tach3 minimum high byte = 0xff default register 0x5a, tach4 minimum low byte = 0xff default register 0x5b, tach4 minimum high byte = 0xff default out-of-limit comparisons once all limits have been programmed, the adt7475 can be enabled for monitoring. the adt7475 measures all voltage and temperature measurements in round-robin format and sets the appropriate status bit for out-of-limit conditions. tach measurements are not part of this round-robin cycle. comparisons are done differently, depending on whether the measured value is being compared to a high or low limit. high limit > comparison performed low limit comparison performed voltage and temperature channels use a window comparator for error detecting and, therefore, have high and low limits. fan speed measurements use only a low limit. this fan limit is needed only in manual fan control mode. analog monitoring cycle time the analog monitoring cycle begins when a 1 is written to the start bit (bit 0) of configuration register 1 (0x40). by default, the adt7475 powers up with this bit set. the adc measures each analog input in turn and, as each measurement is completed, the result is automatically stored in the appropri- ate value register. this round-robin monitoring cycle continues unless disabled by writing a 0 to bit 0 of configuration register 1. as the adc is normally left to free-run in this manner, the time taken to monitor all the analog inputs is normally not of inter- est, because the most recently measured value of any input can be read out at any time. for applications where the monitoring cycle time is impor- tant, it can easily be calculated. the total number of channels measured is ? one dedicated supply voltage input (v ccp pin) ? supply voltage (v cc pin) ? local temperature ? two remote temperatures
adt7475 rev. b | page 21 of 68 as mentioned previously, the adc performs round-robin conversions. the total monitoring cycle time for averaged voltage and temperature monitoring is 146 ms. the total monitoring cycle time for voltage and temperature moni- toring with averaging disabled is 19 ms. the adt7475 is a derivative of the adt7467. as a result, the total conversion time in the adt7475 is the same as the total conversion time of the adt7467. fan tach measurements are made in parallel and are not synchronized with the analog measurements in any way. interrupt status registers the results of limit comparisons are stored in interrupt status register 1 and interrupt status register 2. the status register bit for each channel reflects the status of the last measurement and limit comparison on that channel. if a measurement is within limits, the corresponding status register bit is cleared to 0. if the measurement is out-of-limits, the corresponding status register bit is set to 1. the state of the various measurement channels can be polled by reading the status registers over the serial bus. in bit 7 (ool) of interrupt status register 1 (0x41), 1 means that an out-of-limit event has been flagged in interrupt status register 2. this means that the user needs only to read interrupt status register 2 when this bit is set. alternatively, pin 5 or pin 9 can be configured as an smbalert output. this automatically notifies the system supervisor of an out-of-limit condition. reading the status registers clears the appropriate status bit as long as the error condition that caused the interrupt has cleared. status register bits are sticky. whenever a status bit is set, indicating an out-of-limit condition, it remains set even if the event that caused it has gone away (until read). the only way to clear the status bit is to read the status register after the event has gone away. interrupt status mask registers (0x74 and 0x75) allow individual interrupt sources to be masked from causing an smbalert . however, if one of these masked interrupt sources goes out-of-limit, its associated status bit is set in the interrupt status registers. interrupt status register 1 (0x41) bit 7 (ool) = 1, denotes that a bit in status register 2 is set and that interrupt status register 2 should be read. bit 6 (r2t) = 1, remote 2 temperature high or low limit has been exceeded. bit 5 (lt) = 1, local temperature high or low limit has been exceeded. bit 4 (r1t) = 1, remote 1 temperature high or low limit has been exceeded. bit 2 (v cc ) = 1, v cc high or low limit has been exceeded. bit 1 (v ccp ) = 1, v ccp high or low limit has been exceeded. interrupt status register 2 (0x42) bit 7 (d2) = 1, indicates an open or short on d2+/d2C inputs. bit 6 (d1) = 1, indicates an open or short on d1+/d1C inputs. bit 5 (f4p) = 1, indicates that fan 4 has dropped below minimum speed. alternatively, indicates that the therm limit has been exceeded, if the therm function is used. bit 4 (fan3) = 1, indicates that fan 3 has dropped below minimum speed. bit 3 (fan2) = 1, indicates that fan 2 has dropped below minimum speed. bit 2 (fan1) = 1, indicates that fan 1 has dropped below minimum speed. bit 1 (ovt) = 1, indicates that a therm overtemperature limit has been exceeded. smbalert interrupt behavior the adt7475 can be polled for status, or an smbalert interrupt can be generated for out-of-limit conditions. note how the smbalert output and status bits behave when writing interrupt handler software. sticky status bit high limit tempe r ature cleared on read (temp below limit) temp back in limit (status bit stays set) smbalert 05381-028 figure 25. smbalert and status bit behavior figure 25 shows how the smbalert output and sticky status bits behave. once a limit is exceeded, the corresponding status bit is set to 1. the status bit remains set until the error condition subsides and the status register is read. the status bits are referred to as sticky because they remain set until read by software. this ensures that an out-of-limit event cannot be missed if software is polling the device periodically. note that the smbalert output remains low for the entire duration that a reading is out- of-limit and until the interrupt status register has been read. this has implications for how software handles the interrupt.
adt7475 rev. b | page 22 of 68 handling smbalert interrupts to prevent the system from being tied up servicing interrupts, it is recommended to handle the smbalert interrupt as follows: 1. detect the smbalert assertion. 2. enter the interrupt handler. 3. read the status registers to identify the interrupt source. 4. mask the interrupt source by setting the appropriate mask bit in the interrupt mask registers (0x74 and 0x75). 5. take the appropriate action for a given interrupt source. 6. exit the interrupt handler. 7. periodically poll the status registers. if the interrupt status bit has cleared, reset the corresponding interrupt mask bit to 0. this causes the smbalert output and status bits to behave as shown in . figure 26 sticky status bit high limit temperature cleared on read (temp below limit) temp back in limit (status bit stays set) interrupt mask bit set smbalert 05381-029 interrupt mask bit cleared (smbalert re-armed) figure 26. how masking the interrupt source affects smbalert output masking interrupt sources interrupt mask register 1 (0x74) and interrupt mask register 2 (0x75) allow individual interrupt sources to be masked out to prevent smbalert interrupts. note that masking an interrupt source prevents only the smbalert output from being asserted; the appropriate status bit is set normally. interrupt mask register 1 (0x74) bit 7 (ool) = 1, masks smbalert for any alert condition flagged in interrupt status register 2. bit 6 (r2t) = 1, masks smbalert for remote 2 temperature. bit 5 (lt) = 1, masks smbalert for local temperature. bit 4 (r1t) = 1, masks smbalert for remote 1 temperature. bit 2 (v cc ) = 1, masks smbalert for v channel. cc bit 0 (v ccp ) = 1, masks smbalert for v channel. ccp interrupt mask register 2 (0x75) bit 7 (d2) = 1, masks smbalert for diode 2 errors. bit 6 (d1) = 1, masks smbalert for diode 1 errors. bit 5 (f4p) = 1, masks smbalert for fan 4 failure. if the tach4 pin is being used as the therm input, this bit masks smbalert for a therm event. bit 4 (fan3) = 1, masks smbalert for fan 3. bit 3 (fan2) = 1, masks smbalert for fan 2. bit 2 (fan1) = 1, masks smbalert for fan 1. bit 1 (ovt) = 1, masks smbalert for over temperature (exceeding therm limits). enabling the smbalert interrupt output the smbalert interrupt function is disabled by default. pin 5 or pin 9 can be reconfigured as an smbalert output to signal out-of-limit conditions. table 12. configuring pin 5 as smbalert output register bit setting configuration register 3 (0x78) [0] alert enable = 1 assigning therm functionality to a pin pin 9 on the adt7475 has four possible functions: smbalert , therm , gpio, and tach4. the user chooses the required functionality by setting bit 0 and bit 1 of configuration register 4 (0x7d). table 13. pin 9 configuration bit 1 bit 0 function 0 0 tach4 0 1 therm 1 0 smbalert 1 1 gpio once pin 9 is configured as therm , it must be enabled (bit 1, configuration register 3 (0x78)). therm as an input when therm is configured as an input, the user can time assertions on the therm pin. this can be useful for connect- ing to the prochot output of a cpu to gauge system performance.
adt7475 rev. b | page 23 of 68 the user can also set up the adt7475 so that, when the therm pin is driven low externally, the fans run at 100%. the fans run at 100% for the duration of the time that the therm pin is pulled low. this is done by setting the boost bit (bit 2) in configuration register 3 (0x78) to 1. this works only if the fan is already running, for example, in manual mode when the current duty cycle is above 0x00 or in automatic mode when the temperature is above t . if the temperature is below t or if the duty cycle in manual mode is set to 0x00, pulling the min min therm low externally has no effect. see for more information. figure 27 05381-030 therm t min therm asserted to low as an input: fans do not go to 100% because temperature is below t min . therm asserted to low as an input: fans do not go to 100% because temperature is above t min and fans are already running. figure 27. asserting therm low as an input in automatic fan speed control mode therm timer the adt7475 has an internal timer to measure therm assertion time. for example, the therm input can be con- nected to the prochot output of a pentium 4 cpu to measure system performance. the therm input can also be connected to the output of a trip point temperature sensor. the timer is started on the assertion of the adt7475s therm input and stopped when therm is unasserted. the timer counts therm times cumulatively, that is, the timer resumes counting on the next therm assertion. the therm timer continues to accumulate therm assertion times until the timer is read (it is cleared on read) or until it reaches full scale. if the counter reaches full scale, it stops at that reading until cleared. the 8-bit therm timer status register (0x79) is designed so that the bit 0 is set to 1 on the first therm assertion. once the cumulative therm assertion time has exceeded 45.52 ms, bit 1 of the therm timer is set and bit 0 becomes the lsb of the timer with a resolution of 22.76 ms (see ). figure 28 when using the therm timer, be aware of the following. after a therm timer read (register 0x79), the following happens: 1. the contents of the timer are cleared on read. 2. the f4p bit (bit 5) of interrupt status register 2 needs to be cleared (assuming that the therm timer limit has been exceeded). if the therm timer is read during a therm assertion, the following happens: 1. the contents of the timer are cleared. 2. bit 0 of the therm timer is set to 1 (because a therm assertion is occurring). 3. the therm timer increments from zero. 4. if the therm timer limit (register 0x7a) = 0x00, the f4p bit is set. therm therm timer (reg. 0x79) therm asserted 22.76ms 765 3210 4 000 0001 0 therm timer (reg. 0x79) therm asserted 45.52ms 765 3210 4 000 0010 0 therm timer (reg. 0x79) therm asserted 113.8ms (91.04ms + 22.76ms) 765 3210 4 000 0101 0 therm accumulate therm low assertion times therm accumulate therm low assertion times 0 5381-031 figure 28. understanding the therm timer
adt7475 rev. b | page 24 of 68 generating smbalert interrupts from therm timer events the adt7475 can generate smbalert s when a programma- ble therm timer limit has been exceeded. this allows the system designer to ignore brief, infrequent therm assertions, while capturing longer therm timer events. register 0x7a is the therm timer limit register. this 8-bit register allows a limit from 0 seconds (first therm assertion) to 5.825 seconds to be set before an smbalert is generated. the therm timer value is compared with the contents of the therm timer limit register. if the therm timer value exceeds the therm timer limit value, then the f4p bit (bit 5) of interrupt status register 2 is set, and an smbalert is generated. note that the f4p bit (bit 5) of interrupt mask register 2 (0x75) masks out smbalert s if this bit is set to 1, although the f4p bit of interrupt status register 2 is still set if the therm timer limit is exceeded. figure 29 is a functional block diagram of the therm timer, limit, and associated circuitry. writing a value of 0x00 to the therm timer limit register (0x7a) causes smbalert to be generated on the first therm assertion. a therm timer limit value of 0x01 generates an smbalert once cumulative therm assertions exceed 45.52 ms. 22.76ms 45.52ms 91.04ms 182.08ms 364.16ms 728.32ms 1.457s 2.914s in out reset latch cleared on read f4p bit (bit 5) interrupt mask register 2 (register 0x75) 1 = mask f4p bit (bit 5) comparator 22.76ms 45.52ms 91.04ms 182.08ms 364.16ms 728.32ms 1.457s 2.914s 7 6 543 2 1 0 7 6 543 2 1 0 therm timer limit ( register 0x7a) therm timer (register 0x79) therm timer cleared on read smbalert therm 05381-032 interrupt status register 2 figure 29. functional block diagram of adt7475s therm monitoring circuitry
adt7475 rev. b | page 25 of 68 configuring the a therm e ea behavior 1. configure the relevant pin as the a therm e ea timer input. setting bit 1 ( a therm e ea ) of configuration register 3 (0x78) enables the a therm e ea timer monitoring functionality. this is disabled on pin 9 by default. setting bit 0 and bit 1 (pin9func) of configuration register 4 (0x7d) enables a therm e ea timer/output func- tionality on pin 9 (bit 1, therm e , of configuration register 3, must also be set). pin 9 can also be used as tach4. 2. select the desired fan behavior for a therm e ea timer events. assuming that the fans are running, setting bit 2 (boost bit) of configuration register 3 (0x78) causes all fans to run at 100% duty cycle whenever a therm e ea is asserted. this allows fail-safe system cooling. if this bit is 0, the fans run at their current settings and are not affected by a therm e ea events. if the fans are not already running when a therm e ea is asserted, the fans do not run to full speed. 3. select whether a therm e ea timer events should generate a smbalert e ea interrupts. bit 5 (f4p) of interrupt mask register 2 (0x75), when set, masks out a smbalert e ea s when the a therm e ea timer limit value is exceeded. this bit should be cleared if a smbalert e ea s based on a therm e ea events are required. 4. select a suitable a therm e ea limit value. this value determines whether an a smbalert e ea is generated on the first a therm e ea assertion or only if a cumulative a therm e ea assertion time limit is exceeded. a value of 0x00 causes an a smbalert e ea to be generated on the first a therm e ea assertion. 5. select a a therm e ea monitoring time. this value specifies how often os- or bios-level software checks the a therm e ea timer. for example, bios could read the a therm e ea timer once an hour to determine the cumula- tive a therm e ea assertion time. if, for example, the total a therm e ea assertion time is <22.76 ms in hour 1, >182.08 ms in hour 2, and >2.914 s in hour 3, this can indicate that system performance is degrading significantly because a therm e ea is asserting more frequently on an hourly basis. alternatively, os- or bios-level software can timestamp when the system is powered on. if an smbalert is gen- erated due to the a therm e ea timer limit being exceeded, another timestamp can be taken. the difference in time can be calculated for a fixed a therm e ea timer limit time. for example, if it takes one week for a a therm e ea timer limit of 2.914 seconds to be exceeded and the next time it takes only one hour, this is an indication of a serious degradation in system performance. configuring the therm pin as an output in addition to monitoring a therm e ea as an input, the adt7475 can optionally drive a therm e ea low as an output. in cases where a prochot e ea is bidirectional, a therm e ea can be used to throttle the processor by asserting a prochot e ea . the user can preprogram system-critical thermal limits. if the temperature exceeds a thermal limit by 0.25c, a therm e ea asserts low. if the tempera- ture is still above the thermal limit on the next monitoring cycle, a therm e ea stays low. a therm e ea remains asserted low until the temperature is equal to or below the thermal limit. because the temperature for that channel is measured only once for every monitoring cycle, after a therm e ea asserts, it is guaranteed to remain low for at least one monitoring cycle. the a therm e ea pin can be configured to assert low if the remote 1, local, or remote 2 a therm e ea temperature limit is exceeded by 0.25c. the a therm e ea temperature limit registers are at register 0x6a, register 0x6b, and register 0x6c. setting bit 3 of register 0x5f, register 0x60, and register 0x61 enables the a therm e ea output feature for the remote 1, local, and remote 2 temperature channels, respectively. figure 30 shows how the a therm e ea pin asserts low as an output in the event of a critical over temperature. monitoring cycle temp therm limit 0.25c therm limit therm 05381-033 figure 30. asserting a therm e ea as an output, based on tripping a therm e e limits an alternative method of disabling a therm e ea is to program the a therm e ea temperature limit to ?64c or less in offset 64 mode, or ?128c or less in twos complement mode; that is, for a therm e ea temperature limit values less than ?64c or ?128c, respectively, a therm e ea is disabled.
adt7475 rev. b | page 26 of 68 enabling and disabling therm on individual channels therm can be enabled/disabled for individual or combina- tions of temperature channels using bits [7:5] of configuration register 5 (0x7c). therm hysteresis setting bit 0 of configuration register 7 (0x11) disables therm hysteresis. if therm hysteresis is enabled and therm is disabled (bit 2 of configuration register 4, 0x7d), the therm pin does not assert low when a therm event occurs. if therm hysteresis is disabled and therm is disabled (bit 2 of configuration register 4, 0x7d, and assuming the appropriate pin is config- ured as therm ), the therm pin asserts low when a therm event occurs. if therm and therm hysteresis are both enabled, the therm output asserts as expected. therm operation in manual mode in manual mode, therm events do not cause fans to go to full speed, unless bit 3 of configuration register 6 (0x10) is set to 1. additionally, bit 3 of configuration register 4 (0x7d) can be used to select pwm speed on therm event (100% or maximum pwm). bit 2 in configuration register 4 (0x7d) can be set to disable therm events from affecting the fans. fan drive using pwm control the adt7475 uses pulse-width modulation (pwm) to control fan speed. this relies on varying the duty cycle (or on/off ratio) of a square wave applied to the fan to vary the fan speed. the external circuitry required to drive a fan using pwm control is extremely simple. for 4-wire fans, the pwm drive may need only a pull-up resistor. in many cases, the 4-wire fan pwm input has a built-in pull-up resistor. the adt7475 pwm frequency can be set to a selection of low frequencies or a single high pwm frequency. the low frequency options are usually used for 3-wire fans, while the high frequency option is usua lly used with 4-wire fans. for 3-wire fans, a single n-channel mosfet is the only drive device required. the specifications of the mosfet depend on the maximum current required by the fan being driven. typical notebook fans draw a nominal 170 ma, so sot devices can be used where board space is a concern. in desktops, fans can typically draw 250 ma to 300 ma each. if several fans are driven in parallel from a single pwm output or drive larger server fans, the mosfet must handle the higher current requirements. the only other stipulation is that the mosfet should have a gate voltage drive, v gs < 3.3 v, for direct interfacing to the pwm output pin. the mosfet should also have a low on resistance to ensure that there is not significant voltage drop across the fet, which would reduce the voltage applied across the fan and, therefore, the maximum operating speed of the fan. figure 31 shows how to drive a 3-wire fan using pwm control. 05381-034 adt7475 tach pwm 12v fan q1 ndt3055l 3.3v 12 v 12 v 10k? 4.7k ? 10k ? 10k? 1n4148 figure 31. driving a 3-wire fan using an n-channel mosfet figure 31 uses a 10 k pull-up resistor for the tach signal. this assumes that the tach signal is an open-collector from the fan. in all cases, the tach signal from the fan must be kept below 3.6 v maximum to prevent damaging the adt7475. if in doubt as to whether the fan used has an open-collector or totem pole tach output, use one of the input signal conditioning circuits shown in the fan speed measurement section. figure 32 shows a fan drive circuit using an npn transistor such as a general-purpose mmbt2222. while these devices are inexpensive, they tend to have much lower current han- dling capabilities and higher on resistance than mosfets. when choosing a transistor, care should be taken to ensure that it meets the fans current requirements. ensure that the base resistor is chosen so that the transistor is saturated when the fan is powered on. 05381-035 adt7475 tach tach pwm 12v fan q1 mmbt2222 3.3v 12 v 12 v 665? 4.7k ? 10k ? 10k? 1n4148 figure 32. driving a 3-wire fan using an npn transistor
adt7475 rev. b | page 27 of 68 because 4-wire fans are powered continuously, the fan speed is not switched on or off as with previous pwm driven/powered fans. this enables it to perform better than 3-wire fans, espe- cially for high frequency applications. figure 33 shows a typical drive circuit for 4-wire fans. 05381-036 adt7475 tach pwm 12v, 4-wire fan 3.3v 12 v 12 v 2k ? 4.7k ? 10k ? 10k ? v cc tach tach pwm figure 33. driving a 4-wire fan driving two fans from pwm3 the adt7475 has four tach inputs available for fan speed measurement but only three pwm drive outputs. if a fourth fan is used in the system, it should be driven from the pwm3 output in parallel with the third fan. figure 34 shows how to drive two fans in parallel using low cost npn transistors. figure 35 shows the equivalent circuit using a mosfet. 05381-037 adt7475 pwm3 3.3v 3.3v 12 v 1n4148 q1 mmbt3904 q2 mmbt2222 q3 mmbt2222 10? 10? 2.2k ? 1k? tach3 t a ch4 figure 34. interfacing two fans in parallel to the pwm3 output using low cost npn transistors 05381-038 adt7475 pwm3 tach3 tach4 3.3v 3.3v 3.3 v +v +v tach tach q1 ndt3055l 1n4148 5v or 12v fan 5v or 12v fan 10k ? typical 10k ? typical 10k ? typical figure 35. interfacing two fans in parallel to the pwm3 output using a single n-channel mosfet because the mosfet can handle up to 3.5 a, it is simply a matter of connecting another fan directly in parallel with the first. care should be taken in designing drive circuits with transistors and fets to ensure that the pwm pins are not required to source current and that they sink less than the 8 ma maximum current specified on the data sheet. driving up to three fans from pwm3 tach measurements for fans are synchronized to particular pwm channels; for example, tach1 is synchronized to pwm1. tach3 and tach4 are both synchronized to pwm3, so pwm3 can drive two fans. alternatively, pwm3 can be pro- grammed to synchronize tach2, tach3, and tach4 to the pwm3 output. this allows pwm3 to drive two or three fans. in this case, the drive circuitry looks the same, as shown in figure 37 and figure 38. the sync bit in register 0x62 enables this function. synchronization is not required in high frequency mode when used with 4-wire fans. bit 4 (sync) enhanced acou stics register 1 (0x62) sync = 1, synchronizes tach2, tach3, and tach4 to pwm3. tach inputs pin 4, pin 6, pin 7, and pin 9, when configured as tach inputs, are open-drain tach inputs intended for fan speed measurement. signal conditioning in the adt7475 accommodates the slow rise and fall times typical of fan tachometer outputs. the maxi- mum input signal range is 0 v to 3.6 v. in the event these inputs are supplied from fan outputs that exceed 0 v to 3.6 v, either resistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range. figure 36 to figure 39 show circuits for most common fan tach outputs. if the fan tach output has a resistive pull-up to v cc , it can be connected directly to the fan input, as shown in figure 36 . 05381-039 12v v cc pull-up 4.7k ? typical tach output fan speed counter tach adt7475 figure 36. fan with tach pull-up to v b cc
adt7475 rev. b | page 28 of 68 if the fan output has a resistive pull-up to 12 v, or other voltage greater than 3.6 v, the fan output can be clamped with a zener diode, as shown in figure 37 . the zener diode voltage should be chosen so that it is greater than v ih of the tach input but less than 3.6 v, allowing for the voltage tolerance of the zener. a value between 3 v and 3.6 v is suitable. 0 5381-040 12v v cc pull-up 4.7k ? typical tach output fan speed counter tach adt7475 zd1 1 1 choose zd1 voltage approximately 0.8 v cc . figure 37. fan with tach pull-up to voltage > 3.6 v (for example, 12 v) clamped with zener diode if the fan has a strong pull-up (less than 1 k) to 12 v or a totem-pole output, then a series resistor can be added to limit the zener current, as shown in figure 38 . 1 choose zd1 voltage approximately 0.8 v cc . 05381-041 5v or 12v v cc pull-up typ <1k ? or totem pole tach output fan speed counter tach adt7475 zd1 zener 1 fan r1 10k? figure 38. fan with strong tach pull-up to > v cc or totem-pole output, clamped with zener and resistor alternatively, a resistive attenuator can be used, as shown in figure 39 . r1 and r2 should be chosen such that 2 v < v pull-up r2 /( r pull-up + r1 + r2 ) < 3.6 v the fan inputs can have an input resistance of 160 k to 5.1 k to ground, which should be taken into account when calculat- ing resistor values. with a pull-up voltage of 12 v and pull-up resistor less than 1 k, suitable values for r1 and r2 would be 100 k and 33 k, respectively. this gives a high input voltage of 2.95 v. 05381-042 12v v cc <1k ? tach output fan speed counter tach adt7475 r2 1 1 see text. r1 1 figure 39. fan with strong tach pull-up to > v cc or totem-pole output, attenuated with r1/r2 fan speed measurement the fan counter does not count the fan tach output pulses directly because the fan speed could be less than 1000 rpm and it would take several seconds to accumulate a reasonably large and accurate count. instead, the period of the fan revolution is meas- ured by gating an on-chip 90 khz oscillator into the input of a 16- bit counter for n periods of the fan tach output (see figure 40 ), so the accumulated count is actually proportional to the fan tachometer period and inversely proportional to the fan speed. n, the number of pulses counted, is determined by the set- tings of register 0x7b (tach pulses per revolution register). this register contains two bits for each fan, allowing one, two (default), three, or four tach pulses to be counted. measuring fan tach when the adt7475 starts up, tach measurements are locked. in effect, an internal read of the low byte has been made for each tach input. the net result of this is that all tach readings are locked until the high byte is read from the corresponding tach registers. all tach related interrupts are also ignored until the appropriate high byte is read. once the corresponding high byte has been read, tach measurements are unlocked and interrupts are processed as normal. 05381-043 1 2 3 4 clock pwm tach figure 40. fan speed measurement fan speed measurement registers the fan tachometer readings are 16-bit values consisting of a 2-byte read from the adt7475. register 0x28, tach1 low byte = 0x00 default register 0x29, tach1 high byte = 0x00 default register 0x2a, tach2 low byte = 0x00 default register 0x2b, tach2 high byte = 0x00 default register 0x2c, tach3 low byte = 0x00 default register 0x2d, tach3 high byte = 0x00 default register 0x2e, tach4 low byte = 0x00 default register 0x2f, tach4 high byte = 0x00 default
adt7475 rev. b | page 29 of 68 reading fan speed from the adt7475 the measurement of fan speeds involves a 2-register read for each measurement. the low byte should be read first. this causes the high byte to be frozen until both high and low byte registers have been read, preventing erroneous tach readings. the fan tachometer reading registers report back the number of 11.11 s period clocks (90 khz oscillator) gated to the fan speed counter, from the rising edge of the first fan tach pulse to the rising edge of the third fan tach pulse (assuming two pulses per revolution are being counted). because the device is essentially measuring the fan tach period, the higher the count value, the slower the fan is actually running. a 16-bit fan tachometer read- ing of 0xffff indicates that the fan either has stalled or is running very slowly (<100 rpm). high limit > comparison performed because the actual fan tach period is being measured, falling below a fan tach limit by 1 sets the appropriate status bit and can be used to generate an smbalert . fan tach limit registers the fan tach limit registers are 16-bit values consisting of two bytes. register 0x54, tach1 minimum low byte = 0xff default register 0x55, tach1 minimum high byte = 0xff default register 0x56, tach2 minimum low byte = 0xff default register 0x57, tach2 minimum high byte = 0xff default register 0x58, tach3 minimum low byte = 0xff default register 0x59, tach3 minimum high byte = 0xff default register 0x5a, tach4 minimum low byte = 0xff default register 0x5b, tach4 minimum high byte = 0xff default fan speed measurement rate the fan tach readings are normally updated once every second. the fast bit (bit 3) of configuration register 3 (0x78), when set, updates the fan tach readings every 250 ms. if any of the fans are not being driven by a pwm channel but are powered directly from 5 v or 12 v, their associated dc bit in configuration register 3 should be set. this allows tach readings to be taken on a continuous basis for fans connected directly to a dc source. for optimal results, the associated dc bit should always be set when using 4-wire fans. calculating fan speed assuming a fan with a two pulses per revolution (and two pulses per revolution being measured), fan speed is calculated by the following: fan speed (rpm) = (90,000 60)/ fan tach reading where fan tach reading is the 16-bit fan tachometer reading. example tach1 high byte (register 0x29) = 0x17 tach1 low byte (register 0x28) = 0xff what is fan 1 speed in rpm? fan 1 tach reading = 0x17ff = 6143 (decimal) rpm = (f 60)/fan 1 tach reading rpm = (90,000 60)/6143 fan speed = 879 rpm fan pulses per revolution different fan models can output either 1, 2, 3, or 4 tach pulses per revolution. once the number of fan tach pulses has been determined, it can be programmed into the tach pulses per revolution register (register 0x7b) for each fan. alternatively, this register can be used to determine the number or pulses per revolution output by a given fan. by plotting fan speed measurements at 100% speed with different pulses per revolution setting, the smoothest graph with the lowest ripple determines the correct pulses per revolution value. tach pulses per revolution register bits [1:0] fan 1 default = 2 pulses per revolution. bits [3:2] fan 2 default = 2 pulses per revolution. bits [5:4] fan 3 default = 2 pulses per revolution. bits [7:6] fan 4 default = 2 pulses per revolution. 00 = 1 pulse per revolution 01 = 2 pulses per revolution 10 = 3 pulses per revolution 11 = 4 pulses per revolution
adt7475 rev. b | page 30 of 68 fan spin-up the adt7475 has a unique fan spin-up function. it spins the fan at 100% pwm duty cycle until two tach pulses are detected on the tach input. once two tach pulses have been detected, the pwm duty cycle goes to the expected running value, for example, 33%. the advantage is that fans have different spin-up charac- teristics and take different times to overcome inertia. the adt7475 runs the fans just fast enough to overcome inertia and is quieter on spin-up than fans programmed to spin up for a given spin-up time. fan start-up timeout to prevent the generation of false interrupts as a fan spins up (because it is below running speed), the adt7475 includes a fan start-up timeout function. during this time, the adt7475 looks for two tach pulses. if two tach pulses are not detected, an interrupt is generated. using configuration register 1 (0x40), bit 5 (fspdis), this functionality can be changed (see the disabling fan start-up timeout section). pwm1, pwm2, pwm3 configuration registers (0x5c, 0x5d, and 0x5e) bits [2:0] spin, start-up timeout for pwm1 = 0x5c, pwm2 = 0x5d, and pwm3 = 0x5e. 000 = no start-up timeout 001 = 100 ms 010 = 250 ms default 011 = 400 ms 100 = 667 ms 101 = 1 sec 110 = 2 sec 111 = 4 sec disabling fan start-up timeout although fan startup makes fan spin-ups much quieter than fixed-time spin-ups, the option exists to use fixed spin-up times. setting bit 5 (fspdis) to 1 in configuration register 1 (0x40) disables the spin-up for two tach pulses. instead, the fan spins up for the fixed time as selected in register 0x5c to register 0x5e. pwm logic state the pwm outputs can be programmed high for 100% duty cycle (noninverted) or low for 100% duty cycle (inverted). pwm1 configuration register (0x5c) bit 4 inv 0 = logic high for 100% pwm duty cycle. 1 = logic low for 100% pwm duty cycle. pwm2 configuration register (0x5d) bit 4 inv 0 = logic high for 100% pwm duty cycle. 1 = logic low for 100% pwm duty cycle. pwm3 configuration register (0x5e) bit 4 inv 0 = logic high for 100% pwm duty cycle. 1 = logic low for 100% pwm duty cycle. low frequency mode pwm drive frequency the pwm drive frequency can be adjusted for the application. register 0x5f to register 0x61 configure the pwm frequency for pwm1 to pwm3, respectively. in high frequency mode, the pwm drive frequency is always 22.5 khz. high frequency mode pwm drive setting bit 3 of register 0x5f, register 0x60, and register 0x61 enables high frequency mode for fan 1, fan 2, and fan 3, respectively. pwm frequency registers (0x5f to 0x61) bits [2:0] freq 000 = 11.0 hz 001 = 14.7 hz 010 = 22.1 hz 011 = 29.4 hz 100 = 35.3 hz default 101 = 44.1 hz 110 = 58.8 hz 111 = 88.2 hz fan speed control the adt7475 controls fan speed using automatic mode and manual mode as follows: ? in automatic fan speed control mode, fan speed is automatically varied with temperature and without cpu intervention, once initial parameters are set up. the advantage of this is, if the system hangs, the user is guaranteed that the system is protected from overheating. for more information about how to program the automatic fan speed control loop, see the programming the automatic fan speed control loop section. ? in manual fan speed control mode, the adt7475 allows the duty cycle of any pwm output to be manually adjusted. this can be useful if the user wants to change fan speed at the software level or adjust pwm duty cycle output for test purposes. bits [7:5] of register 0x5c to register 0x5e (pwm configuration) control the behavior of each pwm output.
adt7475 rev. b | page 31 of 68 pwm configuration registers (0x5c to 0x5e) bits [7:5] bhvr 111 = manual mode. once under manual control, each pwm output can be manu- ally updated by writing to register 0x30 to register 0x32 (pwmx current duty cycle registers). programming the pwm current duty cycle registers the pwm current duty cycle registers are 8-bit registers that allow the pwm duty cycle for each output to be set anywhere from 0% to 100% in steps of 0.39%. the value to be programmed into the pwm min register is given by value (decimal) = pwm min /0.39 example 1 : for a pwm duty cycle of 50%, value (decimal) = 50/0.39 = 128 (decimal) value = 128 (decimal) or 0x80 (hex) example 2 : for a pwm duty cycle of 33%, value (decimal) = 33/0.39 = 85 (decimal) value = 85 (decimal) or 0x54 (hex) pwm current duty cycle registers register 0x30, pwm1 current duty cycle = 0x00 (0% default) register 0x31, pwm2 current duty cycle = 0x00 (0% default) register 0x32, pwm3 current duty cycle = 0x00 (0% default) by reading the pwmx current duty cycle registers, the user can keep track of the current duty cycle on each pwm output, even when the fans are running in automatic fan speed control mode or acoustic enhancement mode. see the programming the automatic fan speed control loop section for details. operating from 3.3 v standby the adt7475 has been specifically designed to operate from a 3.3 v stby supply. in computers that support s3 and s5 states, the core voltage of the processor is lowered in these states. when monitoring therm , the therm timer should be disabled during these states. standby mode the adt7475 has been specifically designed to respond to the stby supply. in computers that support s3 and s5 states, the core voltage of the processor is lowered in these states. when monitoring therm , the therm timer should be disabled during these states. when the v ccp voltage drops below the v ccp low limit, the following occurs: 1. status bit 1 (v ccp ) in status register 1 is set. 2. smbalert is generated, if enabled. 3. therm monitoring is disabled. the therm timer should hold its value prior to the s3 or s5 state. once the core voltage, v ccp , goes above the v ccp low limit, everything is re-enabled and the system resumes normal operation. xnor tree test mode the adt7475 includes an xnor tree test mode. this mode is useful for in-circuit test equipment at board-level testing. by applying stimulus to the pins included in the xnor tree, it is possible to detect opens or shorts on the system board. figure 41 shows the signals that are exercised in the xnor tree test mode. the xnor tree test is invoked by setting bit 0 (xen) of the xnor tree test enable register (0x6f). pwm1/xto pwm3 pwm2 tach4 tach3 tach2 t a ch1 0 5381-044 figure 41. xnor tree test
adt7475 rev. b | page 32 of 68 05381-045 adt7475 is powered up has the adt7475 been accessed by a valid smbus transaction? is v ccp above 0.75v? check v ccp runs the fans to full speed has the adt7475 been accessed by a valid smbus transaction? switch off fans start fail-safe timer has the adt7475 been accessed by a valid smbus transaction? fail-safe timer elapses after the fail-safe timeout start up the adt7475 normal ly has the adt7475 been accessed by a valid smbus transaction? y y y y n n n n n y power-on default when the adt7475 is powered up, it polls the v ccp input. if v ccp stays below 0.75 v (the system cpu power rail is not powered up), the adt7475 assumes the functionality of the default registers after the adt7475 is addressed via any valid smbus transaction. if v cc goes high (the system processor power rail is powered up), a fail-safe timer begins to count down. if the adt7475 is not addressed by any valid smbus transactions before the fail- safe timeout (4.6 seconds) lapses, the adt7475 drives the fans to full speed. if the adt7475 is addressed by a valid smbus transaction after this point, the fans stop, and the adt7475 assumes its default settings and begins normal operation. if v ccp goes high (the system processor power rail is powered up), then a fail-safe timer begins to count down. if the adt7475 is addressed by a valid smbus transaction before the fail-safe timeout (4.6 seconds) lapses, then the adt7475 operates normally, assuming the functionality of all the default registers. see the flow chart in figure 42 . figure 42.
adt7475 rev. b | page 33 of 68 programming the automatic fan speed control loop to more efficiently understand the automatic fan speed control loop, it is strongly recommended to use the adt7475 evalua- tion board and software while reading this section. this section provides the system designer with an understanding of the automatic fan control loop, and provides step-by-step guidance on effectively evaluating and selecting critical system parameters. to optimize the system characteristics, the designer needs to give some thought to system configuration, including the number of fans, where they are located, and what tempera- tures are being measured in the particular system. the mechanical or thermal engineer who is tasked with the system thermal characterization should also be involved at the beginning of this process. automatic fan control overview the adt7475 can automatically control the speed of fans based upon the measured temperature. this is done independently of cpu intervention once initial parameters are set up. the adt7475 has a local temperature sensor and two remote temperature channels that can be connected to a cpu on-chip thermal diode (available on intel pentium class and other cpus). these three temperature channels can be used as the basis for automatic fan speed control to drive fans using pulse- width modulation (pwm). automatic fan speed control reduces acoustic noise by optimizing fan speed according to accurately measured temperature. reducing fan speed can also decrease system current consumption. the automatic fan speed control mode is very flexible owing to the number of programmable parameters, including t min and t range . the t min and t range values for a temperature channel, and, therefore, for a given fan are critical because they define the thermal characteristics of the system. the thermal vali- dation of the system is one of the most important steps in the design process, so select these values carefully. figure 43 gives a top-level overview of the automatic fan control circuitry on the adt7475. from a systems-level perspective, up to three system temperatures can be monitored and used to control three pwm outputs. the three pwm outputs can be used to control up to four fans. the adt7475 allows the speed of four fans to be monitored. each temperature channel has a thermal calibration block, allowing the designer to individually configure the thermal characteristics of each temperature channel. for example, the designer can decide to run the cpu fan when cpu temperature increases above 60c and a chassis fan when the local temperature increases above 45c. at this stage, the designer has not assigned these thermal calibration settings to a particular fan drive (pwm) channel. the right side of figure 43 shows controls that are fan-specific. the designer has individual control over parameters such as minimum pwm duty cycle, fan speed failure thresholds, and even ramp control of the pwm outputs. automatic fan control, then, ultimately allows graceful fan speed changes that are less perceptible to the system user. 0 5381-046 mux thermal calibration 0% t min t range thermal calibration 100% 0% t min t range thermal calibration 100% 0% t min t range remote 1 temp local temp remote 2 temp pwm min pwm1 tach1 tach2 tach3 pwm min pwm2 pwm min pwm3 100% pwm generator pwm generator tachometer 3 and 4 measurement tachometer 1 measurement tachometer 2 measurement ramp control (acoustic enhancement) ramp control (acoustic enhancement) ramp control (acoustic enhancement) pwm generator pwm config pwm config pwm config figure 43. automatic fan control block diagram
adt7475 rev. b | page 34 of 68 step 1: hardware configuration during system design, the motherboard sensing and control capabilities should be addressed early in the design stages. decisions about how these capabilities are used should involve the system thermal/mechanical engineer. ask the following questions: 1. what adt7475 functionality will be used? ? pwm2 or smbalert ? ? tach4 fan speed measurement or overtemperature therm function? the adt7475 offers multifunctional pins that can be reconfigured to suit different system requirements and physical layouts. these multifunction pins are software programmable. 2. how many fans will be supported in the system, three or four? this influences the choice of whether to use the tach4 pin or to reconfigure it for the therm function. 3. is the cpu fan to be controlled using the adt7475 or will it run at full speed 100% of the time? if run at 100%, this frees up a pwm output, but the system is louder. 4. where will the adt7475 be physically located in the system? this influences the assignment of the temperature meas- urement channels to particular system thermal zones. for example, locating the adt7475 close to the vrm controller circuitry allows the vrm temperature to be monitored using the local temperature channel. rear chassis front chassis cpu fan sink remote 1 = ambient temp local = vrm temp remote 2 = cpu temp pwm1 pwm2 tach1 tach2 tach3 pwm3 mux thermal calibration 0% t min t range thermal calibration 100% 0% t min t range thermal calibration 100% 0% t min t range pwm min pwm min pwm min 100% 05381-047 pwm generator pwm generator tachometer 3 and 4 measurement tachometer 1 measurement tachometer 2 measurement ramp control (acoustic enhancement) ramp control (acoustic enhancement) ramp control (acoustic enhancement) pwm generator pwm config pwm config pwm config figure 44. hardware configuration example
adt7475 rev. b | page 35 of 68 recommended implementation 1 configuring the adt7475 as in figure 45 provides the system designer with the following features: ? two pwm outputs for fan control of up to three fans. (the front and rear chassis fans are connected in parallel.) ? three tach fan speed measurement inputs. ? v cc measured internally through pin 3. ? cpu core voltage measurement (v core ). ? vrm temperature using local temperature sensor. ? cpu temperature measured using the remote 1 temperature channel. ? ambient temperature measured through the remote 2 temperature channel. ? bidirectional therm pin, which allows the monitoring of prochot output from an intel pentium 4 processor, for example, or can be used as an overtemperature therm output. ? smbalert system interrupt output. 0 5381-048 front chassis fan tach2 adt7475 pwm3 rear c hassis fan ambient temperature tach3 d1+ d1? gnd pwm1 tach1 d2+ d2? therm smbalert sda scl prochot cpu fan cpu ich figure 45. recommended implementation 1
adt7475 rev. b | page 36 of 68 recommended implementation 2 configuring the adt7475 as in figure 46 provides the system designer with the following features: ? three pwm outputs for fan control of up to three fans. (all three fans can be individually controlled.) ? three tach fan speed measurement inputs. ? v cc measured internally through pin 3. ? cpu core voltage measurement (v core ). ? cpu temperature measured using the remote 1 temperature channel. ? ambient temperature measured through the remote 2 temperature channel. ? bidirectional therm pin that allows the monitoring of prochot output from an intel pentium 4 processor, for example, or can be used as an overtemperature therm output. 0 5381-049 front chassis fan tach2 pwm2 adt7475 pwm3 rear chassis fan ambient temperature tach3 d1+ d1? gnd pwm1 tach1 d2+ d2? therm sda scl prochot cpu fan cpu ich figure 46. recommended implementation 2
adt7475 rev. b | page 37 of 68 step 2: configuring the mux after the system hardware configuration is determined, the fans can be assigned to particular temperature channels. not only can fans be assigned to individual channels but the behavior of the fans is also configurable. for example, fans can be run under automatic fan control, manually under software control, or at the fastest speed calculated by multiple temperature channels. the mux is the bridge between temperature measurement channels and the three pwm outputs. bits [7:5] (bhvr) of register 0x5c, register 0x5d, and register 0x5e (pwm configuration registers) control the behavior of the fans connected to the pwm1, pwm2, and pwm3 outputs. the values selected for these bits determine how the mux connects a temperature measurement channel to a pwm output. automatic fan control mux options bits [7:5] (bhvr), register 0x5c, register 0x5d, and register 0x5e. 000 = remote 1 temperature controls pwmx 001 = local temperature controls pwmx 010 = remote 2 temperature controls pwmx 101 = fastest speed calculated by local and remote 2 temperature controls pwmx 110 = fastest speed calculated by all three temperature channel controls pwmx the fastest speed calculated options pertain to controlling one pwm output based on multiple temperature channels. the thermal characteristics of the three temperature zones can be set to drive a single fan. an example is the fan turning on when remote 1 temperature exceeds 60c or when the local temperature exceeds 45c. other mux options bits [7:5] (bhvr), register 0x5c, register 0x5d, and register 0x5e. 011 = pwmx runs full speed. 100 = pwmx disabled (default). 111 = manual mode. pwmx is running under software control. in this mode, pwm current duty cycle registers (0x30 to 0x32) are writable and control the pwm outputs. mux 05381-050 rear chassis front chassis cpu fan sink remote 1 = ambient temp local = vrm temp remote 2 = cpu temp pwm1 pwm2 tach1 tach2 tach3 pwm3 mux thermal calibration 0% t min t range thermal calibration 100% 0% t min t range thermal calibration 100% 0% t min t range pwm min pwm min pwm min 100% pwm generator pwm generator tachometer 3 and 4 measurement tachometer 1 measurement tachometer 2 measurement ramp control (acoustic enhancement) ramp control (acoustic enhancement) ramp control (acoustic enhancement) pwm generator pwm config pwm config pwm config figure 47. assigning temperatur e channels to fan channels
adt7475 rev. b | page 38 of 68 mux configuration example this is an example of how to configure the mux in a system using the adt7475 to control three fans. the cpu fan sink is controlled by pwm1, the front chassis fan is controlled by pwm2, and the rear chassis fan is controlled by pwm3. the mux is configured for the following fan control behavior: ? pwm1 (cpu fan sink) is controlled by the fastest speed calculated by the local (vrm temperature) and remote 2 (processor) temperatures. in this case, the cpu fan sink is also used to cool the vrm. ? pwm2 (front chassis fan) is controlled by the remote 1 temperature (ambient). ? pwm3 (rear chassis fan) is controlled by the remote 1 temperature (ambient). example mux settings bits [7:5] (bhvr), pwm1 configuration register (0x5c). 101 = fastest speed calculated by local and remote 2 temperature controls pwm1 bits [7:5] (bhvr), pwm2 configuration register (0x5d). 000 = remote 1 temperature controls pwm2 bits [7:5] (bhvr), pwm3 configuration register (0x5e). 000 = remote 1 temperature controls pwm3 these settings configure the mux, as shown in figure 48 . 05381-051 rear chassis front chassis cpu fan sink local = vrm temp pwm1 pwm2 tach1 tach2 tach3 pwm3 remote 1 = ambient temp remote 2 = cpu temp thermal calibration 0% t min t range thermal calibration 100% 0% t min t range thermal calibration 100% 0% t min t range pwm min pwm min pwm min 100% mux pwm generator pwm generator tachometer 3 and 4 measurement tachometer 1 measurement tachometer 2 measurement ramp control (acoustic enhancement) ramp control (acoustic enhancement) ramp control (acoustic enhancement) pwm generator pwm config pwm config pwm config figure 48. mux configuration example
adt7475 rev. b | page 39 of 68 step 3: t min settings for thermal calibration channels t min is the temperature at which the fans turn on under automatic fan control. the speed at which the fan runs at t min is programmed later in the process. the t min values chosen are temperature channel specific, for example, 25c for ambient channel, 30c for vrm temperature, and 40c for processor temperature. t min is an 8-bit value, either twos complement or offset 64, that can be programmed in 1c increments. there is a t min register associated with each temperature measure- ment channel: remote 1, local, and remote 2 temperatures. once the t min value is exceeded, the fan turns on and runs at the minimum pwm duty cycle. the fan turns off once the temperature has dropped below t min ? t hyst . to overcome fan inertia, the fan is spun up until two valid tach rising edges are counted. see the fan start-up timeout section for more details. in some cases, primarily for psycho- acoustic reasons, it is desirable that the fan never switch off below t min . bits [7:5] of enhanced acoustics register 1 (0x62), when set, keep the fans running at the pwm minimum duty cycle, if the temperature should fall below t min . t min registers register 0x67, remote 1 temperature t min = 0x5a (90c) register 0x68, local temperature t min = 0x5a (90c) register 0x69, remote 2 temperature t min = 0x5a (90c) enhanced acoustics register 1 (0x62) bit 7 (min3) = 0, pwm3 is off (0% pwm duty cycle) when temperature is below t min ? t hyst . bit 7 (min3) = 1, pwm3 runs at pwm3 minimum duty cycle below t min ? t hyst . bit 6 (min2) = 0, pwm2 is off (0% pwm duty cycle) when temperature is below t min ? t hyst . bit 6 (min2) = 1, pwm2 runs at pwm2 minimum duty cycle below t min ? t hyst . bit 5 (min1) = 0, pwm1 is off (0% pwm duty cycle) when temperature is below t min ? t hyst . bit 5 (min1) = 1, pwm1 runs at pwm1 minimum duty cycle below t min ? t hyst . 05381-052 0% 100% p w m d u t y c y c l e t min rear chassis front chassis cpu fan sink local = vrm temp pwm1 pwm2 tach1 tach2 tach3 pwm3 remote 1 = ambient temp remote 2 = cpu temp mux thermal calibration 0% t min t range thermal calibration 100% 0% t min t range thermal calibration 100% 0% t min t range pwm min pwm min pwm min 100% pwm generator pwm generator tachometer 3 and 4 measurement tachometer 1 measurement tachometer 2 measurement ramp control (acoustic enhancement) ramp control (acoustic enhancement) ramp control (acoustic enhancement) pwm generator pwm config pwm config pwm config figure 49. understanding the t min parameter
adt7475 rev. b | page 40 of 68 step 4: pwm min for each pwm (fan) output pwm min is the minimum pwm duty cycle at which each fan in the system runs. it is also the start speed for each fan under automatic fan control once the temperature rises above t min . for maximum system acoustic benefit, pwm min should be as low as possible. depending on the fan used, the pwm min setting is usually in the 20% to 33% duty cycle range. this value can be found through fan validation. temperature t min 100% pwm min 0% pwm duty cycle 0 5381-055 figure 50. pwm min determines minimum pwm duty cycle more than one pwm output can be controlled from a single temperature measurement channel. for example, remote 1 temperature can control pwm1 and pwm2 outputs. if two different fans are used on pwm1 and pwm2, the fan characteristics can be set up differently. as a result, fan 1 driven by pwm1 can have a different pwm min value than fan 2 connected to pwm2. figure 51 illustrates this as pwm1 min (front fan) turns on at a minimum duty cycle of 20%, while pwm2 min (rear fan) turns on at a minimum of 40% duty cycle. note that both fans turn on at exactly the same temperature, defined by t min . temperature t min 100% pwm1 min 0% pwm duty cycle p w m 1 p w m 2 pwm2 min 05381-056 figure 51. operating two different fans from a single temperature channel programming the pwm min registers the pwm min registers are 8-bit registers that allow the minimum pwm duty cycle for each output to be configured anywhere from 0% to 100%. this allows the minimum pwm duty cycle to be set in steps of 0.39%. the value to be programmed into the pwm min register is given by value (decimal) = pwm min /0.39 example 1: for a minimum pwm duty cycle of 50%, value (decimal) = 50/0.39 = 128 (decimal) value = 128 (decimal) or 80 (hex) example 2: for a minimum pwm duty cycle of 33%, value (decimal) = 33/0.39 = 85 (decimal) value = 85 (decimal) or 54 (hex) pwm min registers register 0x64, pwm1 minimum duty cycle = 0x80 (50% default) register 0x65, pwm2 minimum duty cycle = 0x80 (50% default) register 0x66, pwm3 minimum duty cycle = 0x80 (50% default) note on fan speed and pwm duty cycle the pwm duty cycle does not directly correlate to fan speed in rpm. running a fan at 33% pwm duty cycle does not equate to running the fan at 33% speed. driving a fan at 33% pwm duty cycle actually runs the fan at closer to 50% of its full speed. this is because fan speed in %rpm generally relates to the square root of the pwm duty cycle. given a pwm square wave as the drive signal, fan speed in rpm approximates to 10 % = cycledutypwm fanspeed step 5: pwm max for pwm (fan) outputs pwm max is the maximum duty cycle that each fan in the system runs at under the automatic fan speed control loop. for maxi- mum system acoustic benefit, pwm max should be as low as possible but should be capable of maintaining the processor temperature limit at an acceptable level. if the therm temperature limit is exceeded, the fans are still boosted to 100% for fail-safe cooling. there is a pwm max limit for each fan channel. the default value of all pwm max registers is 0xff.
adt7475 rev. b | page 41 of 68 temperature t min 100% pwm min 0% pwm duty cycle pwm max 05381-057 figure 52. pwm max determines maximum pwm duty cycle below the therm temperature limit programming the pwm max registers the pwm max registers are 8-bit registers that allow the maximum pwm duty cycle for each output to be configured anywhere from 0% to 100%. this allows the maximum pwm duty cycle to be set in steps of 0.39%. the value to be programmed into the pwm max register is given by value (decimal) = pwm max /0.39 example 1: for a maximum pwm duty cycle of 50%, value (decimal) ? 50/0.39 = 128 (decimal) value = 128 (decimal) or 80 (hex) example 2: for a minimum pwm duty cycle of 75%, value (decimal) = 75/0.39 = 192 (decimal) value = 192 (decimal) or c0 (hex) pwm max registers register 0x38, pwm1 maximum duty cycle = 0xff (100% default) register 0x39, pwm2 maximum duty cycle = 0xff (100% default) register 0x3a, pwm3 maximum duty cycle = 0xff (100% default) step 6: t range for temperature channels t range is the range of temperature over which automatic fan control occurs once the programmed t min temperature has been exceeded. t range is the temperature range between pwm min and 100% pwm where the fan speed changes linearly. otherwise stated, it is the line drawn between the t min /pwm min and the (t min + t range )/pwm 100% intersection points. temperature t min 100% pwm min 0% pwm duty cycle t range 05381-058 figure 53. t range parameter affects cooling slope the t range is determined by the following procedure: 1. determine the maximum operating temperature for that channel (for example, 70c). 2. determine, experimentally, the fan speed (pwm duty cycle value) that does not exceed the temperature at the worst- case operating points. (for example, 70c is reached when the fans are running at 50% pwm duty cycle.) 3. determine the slope of the required control loop to meet these requirements. 4. using the adt7475 evaluation software, graphically program and visualize this functionality. ask your local analog devices, inc. representative for details. as pwm min is changed, the automatic fan control slope also changes. t min 100% 33% 0% pwm duty cycle 50% 30c 05381-059 figure 54. adjusting pwm min changes the automatic fan control slope
adt7475 rev. b | page 42 of 68 as t range is changed, the slope also changes. as t range gets smaller, the fans reach 100% speed with a smaller temperature change. 05381-060 t min t min ? hyst 100% 0% pwm duty cycle 30c 40c 10% 45c 54c figure 55. increasing t range changes the afc slope 0 5381-061 100% max pwm 0% pwm duty cycle t range 10% t min ? hyst figure 56. changing pwm max does not change the afc slope selecting t range the t range value can be selected for each temperature channel: remote 1, local, and remote 2 temperatures. bits [7:4] (range) of register 0x5f to register 0x61 define the t range value for each temperature channel. table 14. selecting a t range value bits [7:4] 1 t range (c) 0000 2 0001 2.5 0010 3.33 0011 4 0100 5 0101 6.67 0110 8 0111 10 1000 13.33 1001 16 1010 20 1011 26.67 1100 32 (default) 1101 40 1110 53.33 1111 80 1 register 0x5f configures remote 1 t range ; register 0x60 configures local t range ; register 0x61 configures remote 2 t range . actual changes in pwm output (advanced acoustics settings) while the automatic fan control algorithm describes the general response of the pwm output, the enhanced acoustics registers (0x62 and 0x63) can be used to set/clamp the maximum rate of change of pwm output for a given temperature zone. this means if t range is programmed with a steep afc slope, a relatively small change in temperature can cause a large change in pwm output and an audible change in fan speed, which may be noticeable/ annoying to users. decreasing the pwm outputs maximum rate of change, by programming the smoothing on the appropriate temperature channels (register 0x62 and register 0x63), clamps the fan speeds maximum rate of change in the event of a temperature spike. the pwm duty cycle increases slowly until the pwm duty cycle reaches the appropriate duty cycle as defined by the afc curve. figure 57 shows pwm duty cycle versus temperature for each t range setting. the lower graph shows how each t range setting affects fan speed vs. temperature. as can be seen from the graph, the effect on fan speed is nonlinear.
adt7475 rev. b | page 43 of 68 temperature above t min 0 20406080100120 0 fan speed (% of max) 10 20 30 40 50 60 70 80 90 100 temperature above t min (b) (a) 0 20406080100120 0 pwm duty cycle (%) 10 20 30 40 50 60 70 80 90 100 05381-062 2c 80c 53.3c 40c 32c 26.6c 20c 16c 13.3c 10c 8c 6.67c 5c 4c 3.33c 2.5c 2c 80c 53.3c 40c 32c 26.6c 20c 16c 13.3c 10c 8c 6.67c 5c 4c 3.33c 2.5c figure 57. t range vs. actual fan speed (not pwm drive) profile temperature above t min 0 20 40 60 80 100 120 0 pwm duty cycle (%) 10 20 30 40 50 60 70 80 90 100 temperature above t min (a) (b) 0 20406080100120 0 fan speed (% of max) 10 20 30 40 50 60 70 80 90 100 05381-063 2 c 80c 53.3c 40c 32c 26.6c 20c 16c 13.3c 10c 8c 6.67c 5c 4c 3.33c 2.5c 2c 80c 53.3c 40c 32c 26.6c 20c 16c 13.3c 10c 8c 6.67c 5c 4c 3.33c 2.5c figure 58. t range and % fan speed slopes with pwm min = 20% the graphs in figure 57 assume that the fan starts from 0% pwm duty cycle. clearly, the minimum pwm duty cycle, pwm min , needs to be factored in to see how the loop actually performs in the system. figure 58 shows how t range is affected when the pwm min value is set to 20%. it can be seen that the fan actually runs at about 45% fan speed when the temperature exceeds t min . example: determining t range for each temperature channel the following example shows how the different t min and t range settings can be applied to three different thermal zones. in this example, the following t range values apply: t range = 80c for ambient temperature t range = 53.33c for cpu temperature t range = 40c for vrm temperature this example uses the mux configuration described in step 2: configuring the mux , with the adt7475 connected as shown in figure 48 . both cpu temperature and vrm temperature drive the cpu fan connected to pwm1. ambient temperature drives the front chassis fan and rear chassis fan connected to pwm2 and pwm3. the front chassis fan is configured to run at pwm min = 20%. the rear chassis fan is configured to run at pwm min = 30%. the cpu fan is configured to run at pwm min = 10%. note that the control range for 4-wire fans is much wider than that for 3-wire fans. in many case s, 4-wire fans can start with a pwm drive of as little as 20% or less. in extreme cases, some 3-wire fans do not run unless a pwm drive of 60% or more is applied.
adt7475 rev. b | page 44 of 68 temperature above t min 0 10203040 100 50 60 70 80 90 0 pwm duty cycle (%) 10 20 30 40 50 60 70 80 90 100 temperature above t min 0 fan speed (% max rpm) 10 20 30 40 50 60 70 80 90 100 0 10203040 100 50 60 70 80 90 05381-064 vrm temperature ambient temperature cpu temperature vrm temperature cpu temperature ambient temperature figure 59. t range and % fan speed slopes for vrm, ambient, and cpu temperature channels step 7: t therm for temperature channels t therm is the absolute maximum temperature allowed on a temperature channel. above this temperature, a component such as the cpu or vrm might be operating beyond its safe operating limit. when the temperature measured exceeds t therm , all fans drive at 100% pwm duty cycle (full speed) to provide critical system cooling. the fans remain running at 100% until the temperature drops below t therm ? hysteresis, where hysteresis is the number programmed into the hysteresis registers (0x6d and 0x6e). the default hysteresis value is 4c. the t therm limit should be considered the maximum worst-case operating temperature of the system. because exceeding any t therm limit runs all fans at 100%, it has very negative acoustic effects. ultimately, this limit should be set up as a fail-safe, and the designer should ensure that it is not exceeded under normal system operating conditions. note that t therm limits are nonmaskable and affect the fan speed no matter how automatic fan control settings are configured. this allows some flexibility because a t range value can be selected based on its slope, while a hard limit (such as 70c) can be programmed as t max (the temperature at which the fan reaches full speed) by setting t therm to that limit (for example, 70c). therm registers register 0x6a, remote 1 therm temperature limit = 0x64 (100c default) register 0x6b, local therm temperature limit = 0x64 (100c default) register 0x6c, remote 2 therm temperature limit = 0x64 (100c default) therm hysteresis therm hysteresis on a particular channel is configured via the hysteresis settings in register 0x6d and register 0x6e. for example, setting hysteresis on the remote 1 channel also sets the hysteresis on remote 1 therm . hysteresis registers register 0x6d, remote 1 and local temperature/t min hysteresis register. bits [7:4] (hysr1), remote 1 temperature hysteresis (4c default). bits [3:0] (hysl), local temperature hysteresis (4c default). register 0x6e , remote 2 temperature t min hysteresis register. bits [7:4] (hysr2), remote 2 temperature hysteresis (4c default). because each hysteresis setting is four bits, hysteresis values are programmable from 1c to 15c. it is not recommended that hysteresis values ever be programmed to 0c because this dis- ables hysteresis. in effect, this causes the fans to cycle (during a therm event ) between normal speed and 100% speed or, while operating close to t min , between normal speed and off, creating unsettling acoustic noise.
adt7475 rev. b | page 45 of 68 05381-065 t min p w m d u t y c y c l e 0% 100% t therm t range rear chassis front chassis cpu fan sink local = vrm temp pwm1 pwm2 tach1 tach2 tach3 pwm3 remote 1 = ambient temp remote 2 = cpu temp mux thermal calibration 0% t min t range thermal calibration 100% 0% t min t range thermal calibration 100% 0% t min t range pwm min pwm generator pwm min pwm generator tachometer 3 and 4 measurement pwm min tachometer 1 measurement tachometer 2 measurement ramp control (acoustic enhancement) ramp control (acoustic enhancement) ramp control (acoustic enhancement) pwm generator 100% pwm config pwm config pwm config figure 60. how t therm relates to automatic fan control step 8: t hyst for temperature channels t hyst is the amount of extra cooling a fan provides after the temperature measured has dropped back below t min before the fan turns off. the premise for temperature hysteresis (t hyst ) is that, without it, the fan would merely chatter, or cycle on and off regularly, whenever the temperature is hovering at about the t min setting. the t hyst value chosen determines the amount of time needed for the system to cool down or heat up as the fan turns on and off. values of hysteresis are programmable in the range 1c to 15c. larger values of t hyst prevent the fans from chattering on and off. the t hyst default value is set at 4c. the t hyst setting applies not only to the temperature hysteresis for fan on/off, but the same setting is used for the t therm hysteresis value, described in step 6: t range for temperature channels . therefore, programming register 0x6d and register 0x6e sets the hysteresis for both fan on/off and the therm function. in some applications, it is required that fans not turn off below t min but remain running at pwm min . bits [7:5] of enhanced acoustics register 1 (0x62) allow the fans to be turned off or to be kept spinning below t min . if the fans are always on, the t hyst value has no effect on the fan when the temperature drops below t min . therm hysteresis any hysteresis programmed via register 0x6d and register 0x6e also applies to hysteresis on the appropriate therm channel.
adt7475 rev. b | page 46 of 68 05381-066 rear chassis front chassis cpu fan sink local = vrm temp pwm1 pwm2 tach1 tach2 tach3 pwm3 remote 1 = ambient temp remote 2 = cpu temp mux thermal calibration 0% t min t range thermal calibration 100% 0% t min t range thermal calibration 100% 0% t min t range pwm min pwm min pwm min 100% t min p w m d u t y c y c l e 0% 100% t range t therm ramp control (acoustic enhancement) ramp control (acoustic enhancement) ramp control (acoustic enhancement) pwm generator pwm generator tachometer 3 and 4 measurement tachometer 1 measurement tachometer 2 measurement pwm generator pwm config pwm config pwm config figure 61. the t hyst value applies to fan on/off hysteresis and therm hysteresis enhanced acoustics register 1 (0x62) bit 7 (min3) = 0, pwm3 is off (0% pwm duty cycle) when temperature is below t min ? t hyst . bit 7 (min3) = 1, pwm3 runs at pwm3 minimum duty cycle below t min ? t hyst . bit 6 (min2) = 0, pwm2 is off (0% pwm duty cycle) when temperature is below t min ? t hyst . bit 6 (min2) = 1, pwm2 runs at pwm2 minimum duty cycle below t min ? t hyst . bit 5 (min1) = 0, pwm1 is off (0% pwm duty cycle) when temperature is below t min ? t hyst . bit 5 (min1) = 1, pwm1 runs at pwm1 minimum duty cycle below t min ? t hyst . configuration register 6 (0x10) bit 0 (slow remote 1), 1 slows the ramp rate for pwm changes associated with the remote 1 temperature channel by 4. bit 1 (slow local), 1 slows the ramp rate for pwm changes associated with the local temperature channel by 4. bit 2 (slow remote 2), 1 slows the ramp rate for pwm changes associated with the remote 2 temperature channel by 4. bit 7 (extraslow), 1 slows the ramp rate for all fans by a factor of 39.2%. the following sections list the ramp-up times when the slow bit is set for each temperature monitoring channel. enhanced acoustics register 1 (0x62) bits [2:0] (acou1), select the ramp rate for pwm outputs associated with the remote 1 temperature input. 000 = 37.5 sec 001 = 18.8 sec 010 = 12.5 sec 011 = 7.5 sec 100 = 4.7 sec 101 = 3.1 sec 110 = 1.6 sec 111 = 0.8 sec
adt7475 rev. b | page 47 of 68 enhanced acoustics register 2 (0x63) bits [2:0] (acou3), select the ramp rate for pwm outputs associated with the local temperature channel. 000 = 37.5 sec 001 = 18.8 sec 010 = 12.5 sec 011 = 7.5 sec 100 = 4.7 sec 101 = 3.1 sec 110 = 1.6 sec 111 = 0.8 sec bits [6:4] (acou2), select the ramp rate for pwm outputs associated with the remote 2 temperature input. 000 = 37.5 sec 001 = 18.8 sec 010 = 12.5 sec 011 = 7.5 sec 100 = 4.7 sec 101 = 3.1 sec 110 = 1.6 sec 111 = 0.8 sec when bit 7 of configuration register 6 (0x10) = 1, the ramp rates change to the following values: 000 = 52.2 sec 001 = 26.1 sec 010 = 17.4 sec 011 = 10.4 sec 100 = 6.5 sec 101 = 4.4 sec 110 = 2.2 sec 111 = 1.1 sec setting the appropriate slow bits [2:0] of configuration register 6 (0x10) slows the ramp rate further by a factor of 4.
adt7475 rev. b | page 48 of 68 register tables table 15. adt7475 registers address r/w description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default lockable 0x10 r/w configuration register 6 extraslow v ccp low res res therm in manual slow remote 2 slow local slow remote 1 0x00 0x11 r configuration register 7 res res res res res res res dis therm hys 0x00 0x21 r v ccp reading 9 8 7 6 5 4 3 2 0x00 0x22 r v cc reading 9 8 7 6 5 4 3 2 0x00 0x25 r remote 1 temperature 9 8 7 6 5 4 3 2 0x80 0x26 r local temperature 9 8 7 6 5 4 3 2 0x80 0x27 r remote 2 temperature 9 8 7 6 5 4 3 2 0x80 0x28 r tach1 low byte 7 6 5 4 3 2 1 0 0x00 0x29 r tach1 high byte 15 14 13 12 11 10 9 8 0x00 0x2a r tach2 low byte 7 6 5 4 3 2 1 0 0x00 0x2b r tach2 high byte 15 14 13 12 11 10 9 8 0x00 0x2c r tach3 low byte 7 6 5 4 3 2 1 0 0x00 0x2d r tach3 high byte 15 14 13 12 11 10 9 8 0x00 0x2e r tach4 low byte 7 6 5 4 3 2 1 0 0x00 0x2f r tach4 high byte 15 14 13 12 11 10 9 8 0x00 0x30 r/w pwm1 current duty cycle 7 6 5 4 3 2 1 0 0x00 0x31 r/w pwm2 current duty cycle 7 6 5 4 3 2 1 0 0x00 0x32 r/w pwm3 current duty cycle 7 6 5 4 3 2 1 0 0x00 0x38 r/w pwm1 max duty cycle 7 6 5 4 3 2 1 0 0xff 0x39 r/w pwm2 max duty cycle 7 6 5 4 3 2 1 0 0xff 0x3a r/w pwm3 max duty cycle 7 6 5 4 3 2 1 0 0xff 0x3d r device id register 7 6 5 4 3 2 1 0 0x75 0x3e r company id number 7 6 5 4 3 2 1 0 0x41 0x40 r/w configuration register 1 res todis fspdis vx1 fspd rdy lock strt 0x04 yes 0x41 r interrupt status register 1 ool r2t lt r1t res v cc v ccp res 0x00 0x42 r interrupt status register 2 d2 d1 f4p fan3 fan2 fan1 ovt res 0x00 0x46 r/w v ccp low limit 7 6 5 4 3 2 1 0 0x00 0x47 r/w v ccp high limit 7 6 5 4 3 2 1 0 0xff 0x48 r/w v cc low limit 7 6 5 4 3 2 1 0 0x00 0x49 r/w v cc high limit 7 6 5 4 3 2 1 0 0xff
adt7475 rev. b | page 49 of 68 address r/w description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default lockable 0x4e r/w remote 1 temp low limit 7 6 5 4 3 2 1 0 0x81 0x4f r/w remote 1 temp high limit 7 6 5 4 3 2 1 0 0x7f 0x50 r/w local temp low limit 7 6 5 4 3 2 1 0 0x81 0x51 r/w local temp high limit 7 6 5 4 3 2 1 0 0x7f 0x52 r/w remote 2 temp low limit 7 6 5 4 3 2 1 0 0x81 0x53 r/w remote 2 temp high limit 7 6 5 4 3 2 1 0 0x7f 0x54 r/w tach1 minimum low byte 7 6 5 4 3 2 1 0 0xff 0x55 r/w tach1 minimum high byte 15 14 13 12 11 10 9 8 0xff 0x56 r/w tach2 minimum low byte 7 6 5 4 3 2 1 0 0xff 0x57 r/w tach2 minimum high byte 15 14 13 12 11 10 9 8 0xff 0x58 r/w tach3 minimum low byte 7 6 5 4 3 2 1 0 0xff 0x59 r/w tach3 minimum high byte 15 14 13 12 11 10 9 8 0xff 0x5a r/w tach4 minimum low byte 7 6 5 4 3 2 1 0 0xff 0x5b r/w tach4 minimum high byte 15 14 13 12 11 10 9 8 0xff 0x5c r/w pwm1 configuration register bhvr bhvr bhvr inv res spin spin spin 0x62 yes 0x5d r/w pwm2 configuration register bhvr bhvr bhvr inv res spin spin spin 0x62 yes 0x5e r/w pwm3 configuration register bhvr bhvr bhvr inv res spin spin spin 0x62 yes 0x5f r/w remote 1 t range /pwm1 frequency range range range range hf/lf freq freq freq 0xc4 yes 0x60 r/w local t range /pwm2 frequency range range range range hf/lf freq freq freq 0xc4 yes 0x61 r/w remote 2 t range /pwm3 frequency range range range range hf/lf freq freq freq 0xc4 yes 0x62 r/w enhanced acoustics register 1 min3 min2 min1 sync en1 acou1 acou1 acou1 0x00 yes 0x63 r/w enhanced acoustics register 2 en2 acou2 acou2 acou2 en3 acou3 acou3 acou3 0x00 yes
adt7475 rev. b | page 50 of 68 address r/w description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default lockable 0x64 r/w pwm1 min duty cycle 7 6 5 4 3 2 1 0 0x80 yes 0x65 r/w pwm2 min duty cycle 7 6 5 4 3 2 1 0 0x80 yes 0x66 r/w pwm3 min duty cycle 7 6 5 4 3 2 1 0 0x80 yes 0x67 r/w remote 1 temp t min 7 6 5 4 3 2 1 0 0x5a yes 0x68 r/w local temp t min 7 6 5 4 3 2 1 0 0x5a yes 0x69 r/w remote 2 temp t min 7 6 5 4 3 2 1 0 0x5a yes 0x6a r/w remote 1 therm temp limit 7 6 5 4 3 2 1 0 0x64 yes 0x6b r/w local therm temp limit 7 6 5 4 3 2 1 0 0x64 yes 0x6c r/w remote 2 therm temp limit 7 6 5 4 3 2 1 0 0x64 yes 0x6d r/w remote 1 and local temp/t min hysteresis hysr1 hysr1 hysr1 hysr1 hysl hysl hysl hysl 0x44 yes 0x6e r/w remote 2 temp/t min hysteresis hysr2 hysr2 hysr2 hysr2 res res res res 0x40 yes 0x6f r/w xnor tree test enable res res res res res res res xen 0x00 yes 0x70 r/w remote 1 temperature offset 7 6 5 4 3 2 1 0 0x00 yes 0x71 r/w local temperature offset 7 6 5 4 3 2 1 0 0x00 yes 0x72 r/w remote 2 temperature offset 7 6 5 4 3 2 1 0 0x00 yes 0x73 r/w configuration register 2 shdn conv attn avg res res res res 0x00 yes 0x74 r/w interrupt mask reg. 1 ool r2t lt r1t res v cc v ccp res 0x00 0x75 r/w interrupt mask reg. 2 d2 d1 f4p fan3 fan2 fan1 ovt res 0x00 0x76 r/w extended resolution 1 res res v cc v cc v ccp v ccp res res 0x00 0x77 r/w extended resolution 2 tdm2 tdm2 ltmp ltmp tdm1 tdm1 res res 0x00 0x78 r/w configuration register 3 dc4 dc3 dc2 dc1 fast boost therm alert enable 0x00 yes 0x79 r therm timer status register tmr tmr tmr tmr tmr tmr tmr asrt/tmro 0x00 0x7a r/w therm timer limit register limt limt limt limt limt limt limt limt 0x00 0x7b r/w tach pulses per revolution fan4 fan4 fan3 fan3 fan2 fan2 fan1 fan1 0x55
adt7475 rev. b | page 51 of 68 address r/w description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default lockable 0x7c r/w configuration register 5 r2 therm o/p only local therm o/p only r1 therm o/p only res gpiop gpiod temp offset twos compl 0x01 yes 0x7d r/w configuration register 4 res res bpatt v ccp res max/full on therm therm disable pin9 func pin9func 0x00 yes 0x7e r test register 1 do not write to these registers 0x00 yes 0x7f r test register 2 do not write to these registers 0x00 yes table 16. register 0x10configuration register 6 (power-on default = 0x00) 1 , 2 bit name r/w description [0] slow remote 1 r/w when this bit is set, fan 1 smoothing times are multiplied 4 for remote 1 temperature channel (as defined in register 0x62). [1] slow local r/w when this bit is set, fan 2 smoothing times are multiplied 4 for local temperature channel (as defined in register 0x63). [2] slow remote 2 r/w when this bit is set, fan 3 smoothing times are multiplied 4 for remote 2 temperature channel (as defined in register 0x63). [3] therm in manual r/w when this bit is set, therm is enabled in manual mode. 1 [5:4] reserved n/a reserved. do not write to these bits. [6] v ccp low r/w v ccp lo = 1. when the power is supplied from 3.3 v standby and the core voltage (v ccp ) drops below its v ccp low limit value (register 0x46), the following occurs: ? bit 1 in interrupt status register 1 is set. ? smbalert is generated, if enabled. ? prochot monitoring is disabled. ? everything is re-enabled once v ccp increases above the v ccp low limit. ? when v ccp increases above the low limit: ? prochot monitoring is enabled. ? fans return to their programmed state after a spin-up cycle. [7] extraslow r/w when this bit is set, all fan smoothing times are increased by a further 39.2%. 1 a therm event always overrides any fan setting (even when fans are disabled). 2 this register becomes read-only when the configuration register 1 lock bit is set to 1. any subsequent attempts to write to th is register fail. table 17. register 0x11configuration register 7 (power-on default = 0x00) 1 bit name r/w description [0] dis therm hys r/w setting this bit to 1 disables therm hysteresis. [7:1] reserved n/a reserved. do not write to these bits 1 this register becomes read-only when the configuration register 1 lock bit is set to 1. any subsequent attempts to write to th is register fail. table 18. voltage reading registers (power-on default = 0x00) 1 , 2 register address r/w description 0x21 read-only reflects the voltage measurement at the v ccp input on pin 14 (8 msbs of reading). 1 0x22 read-only reflects the voltage measurement at the v cc input on pin 3 (8 msbs of reading). 2 1 if the extended resolution bits of these readings are also read, the extended resolution registers (reg. 0x76, reg. 0x77) must be read first. once the extended resolution registers are read, the associated msb read ing registers are frozen until read. both the extended resolution registers and the msb registers are frozen. 2 v cc (pin 3) is the supply voltage for the adt7475.
adt7475 rev. b | page 52 of 68 table 19. temperature reading registers (power-on default = 0x80) 1 , 2 register address r/w description 0x25 read-only remote 1 temperature reading (8 msbs of reading). 3 , 4 0x26 read-only local temperature reading (8 msbs of reading). 0x27 read-only remote 2 temperatur e reading (8 msbs of reading). 1 these temperature readings can be in twos complement or offset 64 format; this interpretation is determined by bit 0 of configu ration register 5 (0x7c). 2 if the extended resolution bits of these readings are also read, the extended resolution registers (0x76 and 0x77) must be rea d first. once the extended resolution registers are read, all associated msb reading registers are frozen until read. both the extended resolution registers and the msb registers are frozen. 3 in twos complement mode, a temperature reading of ?128c (0x80) indicates a diode fault (open or short) on that channel. 4 in offset 64 mode, a temperature reading of ?64c (0x00) indicates a diode fault (open or short) on that channel. table 20. fan tachometer reading registers (power-on default = 0x00) 1 register address r/w description 0x28 read-only tach1 low byte. 0x29 read-only tach1 high byte. 0x2a read-only tach2 low byte. 0x2b read-only tach2 high byte. 0x2c read-only tach3 low byte. 0x2d read-only tach3 high byte. 0x2e read-only tach4 low byte. 0x2f read-only tach4 high byte. 1 these registers count the number of 11.11 s periods (based on an internal 90 khz clock) that occur between a number of consecu tive fan tach pulses (default = 2). the number of tach pulses used to count can be changed using the tach pulses per revolution register (0x7b). this allows the fa n speed to be accurately measured. because a valid fan tachometer reading requires that two bytes be read, the low byte must be read first. both the low and high bytes are then frozen until read. at power-on, these registers contain 0x0000 until the first valid fan tach me asurement is read into these registers. this prevents false interrupts from occurring while the fans are spinning up. a count of 0xffff indicates that a fan is one of the following: stalled or blocked (object jamming the fan). failed (internal ci rcuitry destroyed). not populated. (the adt7475 expects to see a fan connected to each tach. if a fan is not connected to that tach, its tach minim um high and low bytes should be set to 0xffff.) alternate function, for example, tach4 reconfigured as a therm pin. table 21. current pwm duty cycle registers (power-on default = 0x00) 1 register address r/w description 0x30 r/w pwm1 current duty cycle (0% to 100% duty cycle = 0x00 to 0xff). 0x31 r/w pwm2 current duty cycle (0% to 100% duty cycle = 0x00 to 0xff). 0x32 r/w pwm3 current duty cycle (0% to 100% duty cycle = 0x00 to 0xff). 1 these registers reflect the pwm duty cycle driving each fan at any given time. when in automatic fan speed control mode, the a dt7475 reports the pwm duty cycles back through these registers. the pwm duty cycle values vary according to temperature in automatic fan speed control mode. duri ng fan startup, these registers report back 0x00. in software mode, the pwm duty cycle outputs can be set to any duty cycle value by writing to these registers . table 22. maximim pwm duty cycle registers (power-on default = 0xff) 1 , 2 register address r/w description 0x38 r/w maximum duty cycle for pw m1 output, default = 100% (0xff). 0x39 r/w maximum duty cycle for pw m2 output, default = 100% (0xff). 0x3a r/w maximum duty cycle for pwm3 output, default = 100% (0xff). 1 this register becomes read-only when the co nfiguration register 1 lock bit is set to 1. any subsequent attempts to write to thi s register fail . 2 these registers set the maximum pwm duty cycle of the pwm output.
adt7475 rev. b | page 53 of 68 table 23. register 0x40configuration register 1 (power-on default = 0x04) bit name r/w description [0] strt 1 , 2 r/w logic 1 enables monitoring and pwm control ou tputs based on the limit settings programmed. logic 0 disables monitoring and pwm control based on the default power-up limit settings. note that the limit values programmed are preserved even if a logic 0 is written to this bit and the default settings are enabled. this bit does not become locked once bit 1 (lock) has been set. [1] lock write once logic 1 locks all limit values to their current settings. on ce this bit is set, all lockable registers become read- only and cannot be modified until the adt7475 is pow ered down and powered up again. this prevents rogue programs such as viruses from modifying critical system limit settings. this bit is lockable. [2] rdy read-only this bit is set to 1 by the adt7475 to indicate only that the device is fully powered up and ready to begin system monitoring. [3] fspd r/w when set to 1, this bit runs all fans at max speed as programmed in the pwm current duty cycle registers (0x30 to 0x32). power-on default = 0. this bit is not locked at any time. [4] vx1 r/w bios should set this bit to a 1 when the adt7475 is configured to measure current from an adi adopt? vrm controller and to measure the cpus core voltage. this bit allows monitoring software to display cpu watts usage. this bit is lockable. [5] fspdis r/w logic 1 disables fan spin-up for two tach pulses. instea d, the pwm outputs go high for the entire fan spin- up timeout selected. [6] todis r/w when this bit is set to 1, the smbus timeout feature is disabled. this allows the adt7475 to be used with smbus controllers that cannot handle smbus timeouts. this bit is lockable. [7] res reserved. 1 bit 0 (strt) of configuration register 1 (0x40) remains writable after the lock bit is set. 2 when monitoring is disabl ed, pwm outputs always go to 100% for thermal protection. table 24. register 0x41interrupt status register 1 (power-on default = 0x00) bit name r/w description [1] v ccp read-only v ccp = 1 indicates that the v ccp high or low limit has been exceeded. this bit is cleared on a read of the status register only if the error condition has subsided. [2] v cc read-only v cc = 1 indicates that the v cc high or low limit has been exceeded. this bit is cleared on a read of the status register only if the error condition has subsided. [4] r1t read-only r1t = 1 indicates that the remote 1 low or high temperature has been exceeded. this bit is cleared on a read of the status register only if the error condition has subsided. [5] lt read-only lt = 1 indicates that the local low or high temperature has been exceeded. this bit is cleared on a read of the status register only if the error condition has subsided. [6] r2t read-only r2t = 1 indicates that the remote 2 low or high temperature has been exceeded. this bit is cleared on a read of the status register only if the error condition has subsided. [7] ool read-only ool = 1 indicates that an out-of-limit event has been latche d in interrupt status register 2. this bit is a logical or of all status bits in interrupt status register 2. so ftware can test this bit in isolation to determine whether any of the voltage, temperature, or fan speed readings represented by interrupt status register 2 are out-of- limit, which saves the need to read interrupt sta tus register 2 every interrupt or polling cycle.
adt7475 rev. b | page 54 of 68 table 25. register 0x42interrupt status register 2 (power-on default = 0x00) bit name r/w description [1] ovt read-only ovt = 1 indicates that one of the therm overtemperature limits has been exceeded. this bit is cleared on a read of the status register when the temperature drops below therm C t . hyst [2] fan1 read-only fan1 = 1 indicates that fan 1 has dropped below minimum speed or has stalled. this bit is not set when the pwm1 output is off. [3] fan2 read-only fan2 = 1 indicates that fan 2 has dropped below minimum speed or has stalled. this bit is not set when the pwm2 output is off. [4] fan3 read-only fan3 = 1 indicates that fan 3 has dropped below minimum speed or has stalled. this bit is not set when the pwm3 output is off. [5] f4p read-only f4p = 1 indicates that fan 4 has dropped below minimum speed or has stalled. this bit is not set when the pwm3 output is off. r/w when pin 9 is programmed as a gpio output, writing to this bit dete rmines the logic output of the gpio. read-only if pin 9 is configured as the therm timer input for therm monitoring, this bit is set when the therm assertion time exceeds the limit programmed in the therm timer limit register (0x7a). [6] d1 read-only d1 = 1 indicates either an ope n or short circuit on the thermal diode 1 inputs. [7] d2 read-only d2 = 1 indicates either an ope n or short circuit on the thermal diode 2 inputs. table 26. voltage limit registers 1 register address r/w description 2 power-on default 0x46 r/w v ccp low limit. 0x00 0x47 r/w v ccp high limit. 0xff 0x48 r/w v cc low limit. 0x00 0x49 r/w v cc high limit. 0xff 1 setting the configuration register 1 lock bit has no effect on these registers. 2 high limits: an interrupt is generated when a value exceeds its high limit (> compar ison); low limits: an interrupt is generat ed when a value is equal to or below its low limit ( comparison). table 27. temperature limit registers 1 register address r/w description 2 power-on default 0x4e r/w remote 1 temperature low limit. 0x81 0x4f r/w remote 1 temperature high limit. 0x7f 0x50 r/w local temperature low limit. 0x81 0x51 r/w local temperature high limit. 0x7f 0x52 r/w remote 2 temperature low limit. 0x81 0x53 r/w remote 2 temperature high limit. 0x7f 1 exceeding any of these temperature limits by 1c causes the appropriate status bit to be set in the inte rrupt status register. setting the configuration register 1 lock bit has no effect on these registers. 2 high limits: an interrupt is generated when a value exceeds its high limit (> compar ison); low limits: an interrupt is generat ed when a value is equal to or below its low limit ( comparison). table 28. fan tachometer limit registers 1 register address r/w description power-on default 0x54 r/w tach1 minimum low byte. 0xff 0x55 r/w tach1 minimum high byte/single-channel adc channel select. 0xff 0x56 r/w tach2 minimum low byte. 0xff 0x57 r/w tach2 minimum high byte. 0xff 0x58 r/w tach3 minimum low byte. 0xff 0x59 r/w tach3 minimum high byte. 0xff 0x5a r/w tach4 minimum low byte. 0xff 0x5b r/w tach4 minimum high byte. 0xff 1 exceeding any of the tach limit registers by 1 indicates that the fan is running too slowly or has stalled. the appropriate st atus bit is set in inte rrupt status register 2 to indicate the fan failure. setting the configuration register 1 lock bit has no effect on these registers.
adt7475 rev. b | page 55 of 68 table 29. register 0x55tach1 minimum high byte (power-on default = 0xff) bits name r/w description [4:0] reserved read-only these bits are reserved when bit 6 of configuration register 2 (0x73) is set (single-channel adc mode). otherwise, these bits represent bits [4:0 ] of the tach1 minimum high byte register. [7:5] scadc r/w when bit 6 of configuration register 2 (0x73) is se t (single-channel adc mode), these bits are used to select the only channel from which the adc makes me asurements. otherwise, th ese bits represent bits [7:5] of the tach1 minimum high byte register. table 30. pwm configuration registers 1 register address r/w p description power-on default 0x5c r/w pwm1 configuration. 0x62 0x5d r/w pwm2 configuration. 0x62 0x5e r/w pwm3 configuration. 0x62 1 these registers become read-only when the configuration register 1 lock bit is set to 1. any su bsequent attempts to write to t hese registers fail. table 31. register 0x5c, register 0x5d , and register 0x5epwm configuratio n registers (power-on default = 0x62) bit name r/w description [2:0] spin r/w these bits control the start-up timeout for pwmx. the pwm output stays high until two valid tach rising edges are seen from the fan. if there is not a valid tach signal during the fan tach measurement directly after the fan start-up timeo ut period, the tach measurement reads 0xffff and interrupt status register 2 reflec ts the fan fault. if the tach minimum high and low bytes contain 0xffff or 0x0000, the interrupt status register 2 bit is not set, even if the fan has not started. 000 = no start-up timeout 001 = 100 ms 010 = 250 ms (default) 011 = 400 ms 100 = 667 ms 101 = 1 sec 110 = 2 sec 111 = 4 sec [4] inv r/w this bit inverts the pwm output. the default is 0, which corresponds to a logic high output for 100% duty cycle. setting this bit to 1 inverts the pwm output so that 100% duty cycl e corresponds to a logic low output. [7:5] bhvr r/w these bits assign each fan to a part icular temperature sensor for localized cooling. 000 = remote 1 temperature controls pwmx (automatic fan control mode). 001 = local temperature controls pwmx (automatic fan control mode). 010 = remote 2 temperature controls pwmx (automatic fan control mode). 011 = pwmx runs full speed. 100 = pwmx disabled (default). 101 = fastest speed calculated by local and remote 2 temperature controls pwmx. 110 = fastest speed calculated by all three temperature channel controls pwmx. 111 = manual mode. pwm duty cycle registers (0x30 to 0x32) become writable.
adt7475 rev. b | page 56 of 68 table 32. temp t range /pwm frequency registers register address r/w 1 description power-on default 0x5f r/w remote 1 t range /pwm1 frequency. 0xc4 0x60 r/w local t range /pwm2 frequency. 0xc4 0x61 r/w remote 2 t range /pwm3 frequency. 0xc4 1 these registers become read-only when the configuration register 1 lock bit is set. any subsequent attemp ts to write to these registers fail. table 33. register 0x5f, register 0x60, and register 0x61temp t range /pwm frequency registers (power-on default = 0xc4) bit name r/w description [2:0] freq r/w these bits control the pwmx frequency. 000 = 11.0 hz 001 = 14.7 hz 010 = 22.1 hz 011 = 29.4 hz 100 = 35.3 hz (default) 101 = 44.1 hz 110 = 58.8 hz 111 = 88.2 hz [3] hf/lf r/w hf/lf =1, enables high frequency pwm output for 4-wire fa ns. once enabled, 3-wire fan-specific settings have no effect (this means, pulse stretching). [7:4] range r/w these bits determine the pwm duty cycl e vs. the temperature slope for automatic fan control. 0000 = 2c 0001 = 2.5c 0010 = 3.33c 0011 = 4c 0100 = 5c 0101 = 6.67c 0110 = 8c 0111 = 10c 1000 = 13.33c 1001 = 16c 1010 = 20c 1011 = 26.67c 1100 = 32c (default) 1101 = 40c 1110 = 53.33c 1111 = 80c
adt7475 rev. b | page 57 of 68 table 34. register 0x62enhanced acoustic s register 1 (power-on default = 0x00) bit name r/w 1 description [2:0] acou1 r/w assuming that pwmx is associated with the remote 1 temperature channel, these bits define the maximum rate of change of the pwmx output for remote 1 te mperature related changes. instead of the fan speed jumping instantaneously to its newly determined speed , it ramps gracefully at the rate determined by these bits. this feature ultimately enhances the acoustics of the fan. when bit 7 of configuration register 6 (0x10) is 0 time slot increase time for 0% to 100% 000 = 1 37.5 sec 001 = 2 18.8 sec 010 = 3 12.5 sec 011 = 4 7.5 sec 100 = 8 4.7 sec 101 = 12 3.1 sec 110 = 24 1.6 sec 111 = 48 0.8 sec when bit 7 of configuration register 6 (0x10) is 1 time slot increase time for 0% to 100% 000 = 1 52.2 sec 001 = 2 26.1 sec 010 = 3 17.4 sec 011 = 4 10.4 sec 100 = 8 6.5 sec 101 = 12 4.4 sec 110 = 24 2.2 sec 111 = 48 1.1 sec [3] en1 r/w when this bit is 1, smoothing is enabled on the remote 1 temperature channel. [4] sync r/w sync = 1 synchronizes fan speed measurements on tach 2, tach3, and tach4 to pwm3. this allows up to three fans to be driven from pwm3 o utput and their speeds to be measured. sync = 0 synchronizes only tach3 and tach4 to pwm3 output. [5] min1 r/w when the adt7475 is in automatic fan control mode, this bit defines whether pwm1 is off (0% duty cycle) or at pwm1 minimum duty cycle when the controlling temperature is below its t min C hysteresis value. 0 = 0% duty cycle below t min C hysteresis. 1 = pwm1 minimum duty cycle below t min C hysteresis. [6] min2 r/w when the adt7475 is in automatic fan speed control mo de, this bit defines whether pwm2 is off (0% duty cycle) or at pwm2 minimum duty cycle when the controlling temperature is below its t min C hysteresis value. 0 = 0% duty cycle below t min C hysteresis. 1 = pwm 2 minimum duty cycle below t min C hysteresis. [7] min3 r/w when the adt7475 is in automatic fan speed control mo de, this bit defines whether pwm3 is off (0% duty cycle) or at pwm3 minimum duty cycle when the controlling temperature is below its t min C hysteresis value. 0 = 0% duty cycle below t min C hysteresis. 1 = pwm3 minimum duty cycle below t min C hysteresis. 1 this register becomes read-only when the configuration register 1 lock bit is set to 1. any subsequent attempts to write to th is register fail.
adt7475 rev. b | page 58 of 68 table 35. register 0x63enhanced acoustic s register 2 (power-on default = 0x00) bit name r/w 1 description [2:0] acou3 r/w assuming that pwmx is associated with the local te mperature channel, these bits define the maximum rate of change of the pwmx output for local temperature related changes. instead of the fan speed jumping instantaneously to its newly determined speed , it ramps gracefully at the rate determined by these bits. this feature ultimately enhances the acoustics of the fan. when bit 7 of configuration register 6 (0x10) is 0 time slot increase time for 0% to 100% 000 = 1 37.5 sec 001 = 2 18.8 sec 010 = 3 12.5 sec 011 = 4 7.5 sec 100 = 8 4.7 sec 101 = 12 3.1 sec 110 = 24 1.6 sec 111 = 48 0.8 sec when bit 7 of configuration register 6 (0x10) is 1 time slot increase time for 0% to 100% 000 = 1 52.2 sec 001 = 2 26.1 sec 010 = 3 17.4 sec 011 = 4 10.4 sec 100 = 8 6.5 sec 101 = 12 4.4 sec 110 = 24 2.2 sec 111 = 48 1.1 sec [3] en3 r/w when this bit is 1, smoothing is enabled on the local temperature channel. [6:4] acou2 r/w assuming that pwmx is associated with the remote 2 temperature channel, these bits define the maximum rate of change of the pw mx output for remote 2 tempera ture related changes. instead of the fan speed jumping instantaneously to its newly de termined speed, it ramps gracefully at the rate determined by these bits. this feature ultimately enhances the acoustics of the fan. when bit 7 of configuration register 6 (0x10) is 0 time slot increase time for 0% to 100% 000 = 1 37.5 sec 001 = 2 18.8 sec 010 = 3 12.5 sec 011 = 4 7.5 sec 100 = 8 4.7 sec 101 = 12 3.1 sec 110 = 24 1.6 sec 111 = 48 0.8 sec when bit 7 of configuration register 6 (0x10) is 1 time slot increase time for 0% to 100% 000 = 1 52.2 sec 001 = 2 26.1 sec 010 = 3 17.4 sec 011 = 4 10.4 sec 100 = 8 6.5 sec 101 = 12 4.4 sec 110 = 24 2.2 sec 111 = 48 1.1 sec [7] en2 r/w when this bit is 1, smoothing is enabled on the remote 2 temperature channel. 1 this register becomes read-only when the configuration register 1 lock bit is set to 1. any subsequent attempts to write to th is register fail.
adt7475 rev. b | page 59 of 68 table 36. pwm minimum duty cycle registers register address r/w 1 description power-on default 0x64 r/w pwm1 minimum duty cycl e. 0x80 (50% duty cycle) 0x65 r/w pwm2 minimum duty cycle. 0x80 (50% duty cycle) 0x66 r/w pwm3 minimum duty cycle. 0x80 (50% duty cycle) 1 these registers become read -only when the adt7475 is in automatic fan control mode. table 37. register 0x64, register 0x65, re gister 0x66pwm minimum duty cycle register s (power-on default = 0x80; 50% duty cycle ) bit name r/w 1 description [7:0] pwm duty cycle r/w these bits define the pwm min duty cycle for pwmx. 0x00 = 0% duty cycle (fan off ). 0x40 = 25% duty cycle. 0x80 = 50% duty cycle. 0xff = 100% duty cycle (fan full speed). 1 these registers become read -only when the adt7475 is in automatic fan control mode. table 38. t min registers 1 register address r/w 2 description power-on default 0x67 r/w remote 1 temperature t min . 0x5a (90c) 0x68 r/w local temperature t min . 0x5a (90c) 0x69 r/w remote 2 temperature t min . 0x5a (90c) 1 these are the t min registers for each temperature channel. when the temperature measured exceeds t min , the appropriate fan runs at minimum speed and increases with temperature according to t range . 2 these registers become read-only when the configuration register 1 lock bit is set. any subsequent attemp ts to write to these registers fail. table 39. therm temperature limit registers 1 register address r/w 2 description power-on default 0x6a r/w remote 1 therm temperature limit. 0x64 (100c) 0x6b r/w local therm temperature limit. 0x64 (100c) 0x6c r/w remote 2 therm temperature limit. 0x64 (100c) 1 if any temperature measured exceeds its therm limit, all pwm outputs drive their fans at 100% duty cycle. this is a fail-safe mechanism incorporated to cool the system in the event of a critical overtemperature. it also ensures some level of cooling in the event that software or hardware locks up. if set to 0x80, this feature is disabled. the pwm output remains at 100% until the temperature drops below a therm limit ? hysteresis. if the therm pin is programmed as an output, then exceeding these limits by 0.25c can cause the therm pin to assert low as an output. 2 these registers become read-only when the configuration register 1 lock bit is set to 1. any subsequent attempts to write to t hese registers fail. table 40. temperature/t min hysteresis registers 1 register address bit name r/w 2 description power-on default 0x6d r/w remote 1 and local temperature hysteresis. 0x44 hysl [3:0] local temperature hysteresis. 0c to 15c of hysteresis can be applied to the local temperature and afc loops. hysr1 [7:4] remote 1 temperature hysteresis. 0c to 15c of hysteresis can be applied to the remote 1 temperature and afc loops. 0x6e r/w remote 2 temperature hysteresis. 0x40 hysr2 [7:4] local temperature hysteresis. 0c to 15c of hysteresis can be applied to the local temperature and afc loops. 1 each 4-bit value controls the amount of temperature hysteresis applied to a particular temperature channel. once the temperatu re for that channel falls below its t min value, the fan remains running at pwm min duty cycle until the temperature = t min ? hysteresis. up to 15c of hysteresis can be assigned to any temperature channel. the hysteresis value chosen also applies to that temperature channel, if its therm limit is exceeded. the pwm output being controlled goes to 100%, if the therm limit is exceeded and remains at 100 % until the temperature drops below therm ? hysteresis. for acoustic reasons, it is recommended that the hysteresis value not be programmed to less than 4c. setting the hysteresis value lower than 4c causes the fan to switch on and off regul arly when the temperature is close to t min . 2 these registers become read-only when the configuration register 1 lock bit is set to 1. any subsequent attempts to write to t hese registers fail.
adt7475 rev. b | page 60 of 68 table 41. xnor tree test enable register register address bit name r/w 1 description power-on default 0x6f r/w xnor tree test enable register. 0x00 xen [0] if the xen bit is set to 1, the device enters the xnor tree test mode. clearing the bit removes the device from the xnor tree test mode. res [7:1] unused. do not write to these bits. 1 this register becomes read-only when the co nfiguration register 1 lock bit is set to 1. any subsequent attempts to write to thi s register fail. table 42. remote 1 temperature offset register register address bit r/w 1 description power-on default 0x70 [7:0] r/w remote 1 temperature offset. 0x00 allows a twos complement offset value to be automatically added to or subtracted from the remote 1 temperature reading. this is to compensate for any inherent system offsets such as pcb trace resistance. lsb value = 0.5c. 1 this register becomes read-only when the co nfiguration register 1 lock bit is set to 1. any subsequent attempts to write to thi s register fail. table 43. local temperature offset register register address bit r/w 1 description power-on default 0x71 [7:0] r/w local temperature offset. 0x00 allows a twos complement offset value to be automatically added to or subtracted from the local temperature reading. lsb value = 0.5c. 1 this register becomes read-only when the co nfiguration register 1 lock bit is set to 1. any subsequent attempts to write to thi s register fail. table 44. remote 2 temperature offset register 1 register address bit r/w description power-on default 0x72 [7:0] r/w remote 2 temperature offset. 0x00 allows a twos complement offset value to be automatically added to or subtracted from the remote 2 temperature reading. this is to compensate for any inherent system offsets such as pcb trace resistance. lsb value = 0.5c. 1 this register becomes read-only when the configuration register 1 lock bit is set to 1. any subsequent attempts to write to th is register fail.
adt7475 rev. b | page 61 of 68 table 45. register 0x73configuration register 2 (power-on default = 0x00) bit name r/w 1 description [0:3] res reserved. [4] avg r/w avg = 1, averaging on the temperature and voltage measurements is turned off. this allows measurements on each channel to be made much faster. [5] attn r/w attn = 1, the adt7475 removes the attenuators from the v ccp input. the v ccp input can be used for other functions such as connecting up external sensors. [6] conv r/w conv = 1, the adt7475 is put into a single -channel adc conversion mode. in this mode, the adt7475 can be made to read continuously from one input only, for example, remote 1 temperature. the appropriate adc channel is selected by writing to bits [7:5] of tach1 minimum high byte register (0x55). register 0x55, bits [7:5] 000 reserved 001 v ccp 010 v cc (3.3 v) 011 reserved 100 reserved 101 remote 1 temperature 110 local temperature 111 remote 2 temperature [7] shdn r/w shdn = 1, adt7475 goes into shutdown mode. all pwm outputs assert low (or high depending on state of the inv bit) to switch off all fans. the pwm current duty cycle registers read 0x00 to indicate that the fans are not being driven. 1 this register becomes read-only when the configuration register 1 lock bit is set to 1. any subsequent attempts to write to th is register fail. table 46. register 0x74interrupt mask register 1 (power-on default <7:0> = 0x00) bit name r/w description [1] v ccp r/w v ccp = 1, masks smbalert for out-of-limit conditions on the v channel. ccp [2] v cc r/w v cc = 1, masks smbalert for out-of-limit conditions on the v channel. cc [4] r1t r/w r1t = 1, masks smbalert for out-of-limit conditions on the remote 1 temperature channel. [5] lt r/w lt = 1, masks smbalert for out-of-limit conditions on the local temperature channel. [6] r2t r/w r2t = 1, masks smbalert for out-of-limit conditions on the remote 2 temperature channel. [7] ool r/w ool = 0, when one or more alerts are generated in interrupt status register 2, assuming that all the mask bits in the interrupt mask register 2 (0x75) = 1, smbalert is still asserted. ool = 1, when one or more alerts are generated in interrupt status register 2, assuming that all the mask bits in the interrupt mask register 2 (0x75) = 1, smbalert is not asserted. table 47. register 0x75interrupt mask register 2 (power-on default <7:0> = 0x00) bit name r/w description [1] ovt read only ovt = 1, masks smbalert for overtemperature therm conditions. [2] fan1 r/w fan1 = 1, masks smbalert for a fan 1 fault. [3] fan2 r/w fan2 = 1, masks smbalert for a fan 2 fault. [4] fan3 r/w fan3 = 1, masks smbalert for a fan 3 fault. [5] f4p r/w f4p = 1, masks smbalert for a fan 4 fault. if the tach4 pin is being used as the therm input, this bit masks smbalert for a therm timer event. [6] d1 r/w d1 = 1, masks smbalert for a diode open or short on a remote 1 channel. [7] d2 r/w d2 = 1, masks smbalert for a diode open or short on a remote 2 channel.
adt7475 rev. b | page 62 of 68 table 48. register 0x76extended resolution register 1 1 bit name r/w description [3:2] v ccp r/w v ccp lsbs. holds the 2 lsbs of the 10-bit v ccp measurement. [5:4] v cc r/w v cc lsbs. holds the 2 lsbs of the 10-bit v cc measurement. 1 if this register is read, this register and the registers holding the ms b of each reading are frozen until read. table 49. register 0x77extended resolution register 2 1 bit name r/w description [3:2] tdm1 r/w remote 1 temperature lsbs. holds the 2 lsbs of the 10-bit remote 1 temperature measurement. [5:4] ltmp r/w local temperature lsbs. holds the 2 lsbs of the 10-bit local temperature measurement. [7:6] tdm2 r/w remote 2 temperature lsbs. holds the 2 lsbs of the 10-bit remote 2 temperature measurement. 1 if this register is read, this register and the registers holding the ms b of each reading are frozen until read. table 50. register 0x78configuration register 3 (power-on default = 0x00) bit name r/w 1 description [0] alert enable r/w alert = 1, pin 5 (pwm2/ smbalert ) is configured as an smbalert interrupt output to indicate out- of-limit error conditions. [1] therm r/w therm enable = 1 enables therm timer monitoring functionality on pin 9. also determined by bit 0 and bit 1 (pin9func) of configuration register 4. when therm is asserted, if the fans are running and the boost bit is set, the fans run at full speed. alternatively, therm can be programmed so that a timer is triggered to time how long therm has been asserted. [2] boost r/w when therm is an input and boost = 1, assertion of therm causes all fans to run at the maximum programmed duty cycle for fail-safe cooling. [3] fast r/w fast = 1, enables fast tach measurements on all channels. this increases the tach measurement rate from once per second to once every 250 ms (4). [4] dc1 r/w dc1 = 1, enables tach measurements to be contin uously made on tach1. fans must be driven by dc. setting this bit prevents pulse stretching because it is not required for dc-driven motors. [5] dc2 r/w dc2 = 1, enables tach measurements to be contin uously made on tach2. fans must be driven by dc. setting this bit prevents pulse stretching because it is not required for dc-driven motors. [6] dc3 r/w dc3 = 1, enables tach measurements to be contin uously made on tach3. fans must be driven by dc. setting this bit prevents pulse stretching because it is not required for dc-driven motors. [7] dc4 r/w dc4 = 1, enables tach measurements to be contin uously made on tach4. fans must be driven by dc. setting this bit prevents pulse stretching because it is not required for dc-driven motors. 1 this register becomes read-only when the configuration register 1 lock bit is set to 1. any subsequent attempts to write to th is register fail. table 51. register 0x79 therm timer status register (power-on default = 0x00) bit name r/w description [0] asrt/ tmr0 read-only this bit is set high on the assertion of the therm input and is cleared on read. if the therm assertion time exceeds 45.52 ms, this bit is set and becomes the lsb of the 8-bit tmr reading. this allows therm assertion times from 45.52 ms to 5.82 sec to be reported back with a resolution of 22.76 ms. [7:1] tmr read-only times how long therm input is asserted. these seven bits read zero until the therm assertion time exceeds 45.52 ms. table 52. register 0x7a therm timer limit register (power-on default = 0x00) bit name r/w description [7:0] limt r/w sets the maximum therm assertion length allowed before an interrupt is generated. this is an 8-bit limit with a resolution of 22.76 ms allowing therm assertion limits of 45.52 ms to 5.82 sec to be programmed. if the therm assertion time exceeds this limit, bit 5 (f4p) of interrupt status register 2 (0x42) is set. if the limit value is 0x00, an interrupt is generated immediately on the assertion of the therm input.
adt7475 rev. b | page 63 of 68 table 53. register 0x7btach pulses per revo lution register (power-on default = 0x55) bit name r/w description [1:0] fan1 r/w sets the number of pulses to be counted when measuring fan 1 speed. can be used to determine fan pulses per revolution for an unknown fan type. pulses counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 [3:2] fan2 r/w sets the number of pulses to be counted when measuring fan 2 speed. can be used to determine fan pulses per revolution for an unknown fan type. pulses counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 [5:4] fan3 r/w sets the number of pulses to be counted when measuring fan 3 speed. can be used to determine fan pulses per revolution for an unknown fan type. pulses counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 [7:6] fan4 r/w sets the number of pulses to be counted when measuring fan 4 speed. can be used to determine fan pulses per revolution for an unknown fan type. pulses counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4 table 54. register 0x7cconfiguration register 5 (power-on default = 0x01) bit name r/w 1 description [0] twos compl r/w twos complement = 1, sets the temperature range to twos complement temperature range. twos complement = 0, changes the temperature rang e to offset 64. when this bit is changed, the adt7475 interprets all relevant temperature re gister values as defined by this bit. [1] tempoffset r/w tempoffset = 0, sets offset range to ?63c to +64c with 0.5c resolution. tempoffset = 1, sets offset range to ?63c to +127c with 1c resolution. these settings apply to the 0x70, 0x71, and 0x72 regi sters (remote 1, local, and remote 2 temperature offset registers). [2] gpiod r/w gpio direction. when the gpio function is enabled, this determines whether the gpio is an input (0) or an output (1). [3] gpiop r/w gpio polarity. when the gpio function is enab led and is programmed as an output, this bit determines whether the gpio is active low (0) or high (1). [4] res reserved. [5] r1 a therm e ea r/w r1 a therm e ea = 0 , a therm e ea temperature limit functionality is enable d for the remote 1 temperature channel. a therm e ea can also be disabled on any channel by the following: in offset 64 mode, writing ?64c to the appropriate a therm e ea temperature limit. in twos complement mode, writing ?128c to the appropriate a therm e ea temperature limit.
adt7475 rev. b | page 64 of 68 bit name r/w 1 description [6] local therm r/w local therm = 0, therm temperature limit functionality enab led for local temperature channel. therm can also be disabled on any channel by the following: in offset 64 mode, writing ?64c to the appropriate therm temperature limit. in twos complement mode, writing ?128c to the appropriate therm temperature limit. [7] r2 therm r/w r2 therm = 0, therm temperature limit functionality enabled for remote 2 temperature channel. therm can also be disabled on any channel by the following: in offset 64 mode, writing ?64?c to the appropriate therm temperature limit. in twos complement mode, writing ?128?c to the appropriate therm temperature limit. 1 this register becomes read-only when the configuration register 1 lock bit is set to 1. any further attempts to write to this register have no effect. table 55. register 0x7dconfiguration register 4 (power-on default = 0x00) bit name r/w 1 description [1:0] pin9func r/w these bits set the functionality of pin 9: 00 = tach4 (default) 01 = bidirectional therm 10 = smbalert 11 = gpio [2] therm disable r/w therm disable = 0, therm overtemperature output is enabled assuming therm is correctly configured (register 0x78, regist er 0x7c, and register 0x7d). therm disable = 1, therm overtemperature output is disabled on all channels. therm can also be disabled on any channel by the following: in offset 64 mode, writing ?64c to the appropriate therm temperature limit in twos complement mode, writing ?128c to the appropriate therm temperature limit [3] max/full on therm r/w max/full on therm = 0. when therm limit is exceeded, fans go to full speed. max/full on therm = 1. when therm limit is exceeded, fans go to maximum speed as defined in register 0x38, register 0x39, and register 0x3a. [4:7] res unused. [5] bpattv ccp r/w bypass v ccp attenuator. when set, the measurement scale for this channel changes from 0 v (0x00) to 2.2965 v (0xff) . [6:7] res unused. 1 this register becomes read-only when the configuration register 1 lock bit is set to 1. any subsequent attempts to write to th is register fail. table 56. register 0x7emanufacturers te st register 1 (power-on default = 0x00) bit name r/w description [7:0] reserved read-only manufacturers test register. these bits are reserved for manufacturers test purposes and should not be written to under normal operation. table 57. register 0x7fmanufacturers te st register 2 (power-on default = 0x00) bit name r/w description [7:0] reserved read-only manufacturers test register. these bits are reserved for manufacturers test purposes and should not be written to under normal operation.
adt7475 rev. b | page 65 of 68 outline dimensions compliant to jedec standards mo-137-ab 16 9 8 1 pin 1 seating plane 0.010 0.004 0.012 0.008 0.025 bsc 0.010 0.006 0.050 0.016 8 0 coplanarity 0.004 0.065 0.049 0.069 0.053 0.197 0.193 0.189 0.158 0.154 0.150 0.244 0.236 0.228 figure 62. 16-lead shrink small outline package [qsop] (rq-16) dimensions shown in inches ordering guide model temperature range package description package option adt7475arqz 1 C40c to +125c 16-lead qsop rq-16 ADT7475ARQZ-REEL 1 C40c to +125c 16-lead qsop rq-16 ADT7475ARQZ-REEL7 1 C40c to +125c 16-lead qsop rq-16 eval-adt7475eb evaluation board 1 z = rohs compliant part.
adt7475 rev. b | page 66 of 68 notes
adt7475 rev. b | page 67 of 68 notes
adt7475 rev. b | page 68 of 68 notes ?2005C2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05381-0-11/07(b)

▲Up To Search▲

Price & Availability of ADT7475ARQZ-REEL

	To Download ADT7475ARQZ-REEL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .